NXP Semiconductors K22F series, Reference Manual, Page: 947 / 1407

FTM counter
0
3
4 0 1 2
3 4 0 1 2 3 4 0 1
2
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
channel (n) output
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
channel (n)
match
counter
overflow
FTM counting is up.
Channel (n) is in high-true EPWM mode.
PS[2:0] = 001
CNTIN = 0x0000
MOD = 0x0004
CnV = 0x0002
prescaler counter
Figure 39-2. Notation used
39.4.1 Clock source
The FTM has only one clock domain: the system clock.
39.4.1.1 Counter clock source
The CLKS[1:0] bits in the SC register selects clock sources for the FTM counter or
disables the FTM counter. After any chip reset, CLKS[1:0] = 0:0 so no clock source is
selected.
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
The fixed frequency clock is an alternative clock source for the FTM counter that allows
the selection of a clock other than the system clock or an external clock. This clock input
is defined by chip integration; see the chip-specific FTM information for further details.
Due to FTM hardware implementation limitations, the frequency of the fixed frequency
clock must not exceed 1/2 of the system clock frequency.
Chapter 39 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 947