NXP Semiconductors K22F series, Reference Manual, Page: 80 / 1407

3.3.10.3 EWM_OUT pin state in low power modes
When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its
previous state before entering Wait or Stop mode. When the CPU enters Run mode from
Power Down, the pin returns to its reset state.
3.3.11 Watchdog Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
WDOG
Mode
Controller
Peripheral
bridge 0
Register
access
Figure 3-15. Watchdog configuration
Table 3-24. Reference links to related information
Topic Related module Reference
Full description Watchdog Watchdog
System memory map System memory map
Clocking Clock distribution
Power management Power management
Mode Controller (MC)
3.3.11.1 WDOG clocks
This table shows the WDOG module clocks and the corresponding chip clocks.
Table 3-25. WDOG clock connections
Module clock Chip clock
LPO Oscillator 1 kHz LPO Clock
Table continues on the next page...
System modules
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
80 NXP Semiconductors