NXP Semiconductors K22F series, Reference Manual, Page: 616 / 1407

For example, consider the following scenario:
• Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads
enabled.
• The core requests four sequential longwords in back-to-back requests, meaning there
are no core cycle delays except for stalls waiting for flash memory data to be
returned.
• None of the data is already stored in the cache or speculation buffer.
In this scenario, the sequence of events for accessing the four longwords is as follows:
1. The first longword read requires 4 to 7 core clocks. See Wait states for more
information.
2. Due to the 64-bit data bus of the flash memory, the second longword read takes only
1 core clock because the data is already available inside the FMC. While the data for
the second longword is being returned to the core, the FMC also starts reading the
third and fourth longwords from the flash memory.
3. Accessing the third longword requires 3 core clock cycles. The flash memory read
itself takes 4 clocks, but the first clock overlaps with the second longword read.
4. Reading the fourth longword, like the second longword, takes only 1 clock due to the
64-bit flash memory data bus.
28.5.4 Flash Access Control (FAC) Function
The Flash Access Control (FAC) is a configurable memory protection scheme optimized
to allow end users to use software libraries while offering programmable restrictions to
these libraries. The flash memory is divided into equal size segments that provide
protection to proprietary software libraries. The protection of these segments is
controlled: the FAC provides a cycle-by-cycle evaluation of the access rights for each
transaction routed to the on-chip flash memory. Two levels of vendors can add their
proprietary software to a device; FAC protection of segments for each level are defined
once, using the PGMONCE command.
Flash access control aligns to the 3 privilege levels supported by ARM Cortex-M family
products:
• Most secure state is supervisor/privileged secure: allows execute-only and provides
supervisor-only access control.
• Mid-level state is execute-only.
• Unsecure state is where no access control states are set.
Features:
• Lightweight access control logic for on-chip flash memory
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
616 NXP Semiconductors