NXP Semiconductors K22F series, Reference Manual, Page: 1137 / 1407

SPIx_CTARn field descriptions (continued)
Field Description
Table 45-2. SPI SCK Duty Cycle
(continued)
DBR CPHA PBR SCK Duty Cycle
1 0 11 43/57
1 1 00 50/50
1 1 01 66/33
1 1 10 60/40
1 1 11 57/43
0 The baud rate is computed normally with a 50/50 duty cycle.
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
30–27
FMSZ Frame Size
The number of bits transferred per frame is equal to the FMSZ value plus 1. Regardless of the
transmission mode, the minimum valid frame size value is 4.
26
CPOL
Clock Polarity
Selects the inactive state of the Serial Communications Clock (SCK). This bit is used in both master and
slave mode. For successful communication between serial devices, the devices must have identical clock
polarities. When the Continuous Selection Format is selected, switching between clock polarities without
stopping the module can cause errors in the transfer due to the peripheral device interpreting the switch of
clock polarity as a valid clock edge.
NOTE: In case of Continuous SCK mode, when the module goes in low power mode(disabled), inactive
state of SCK is not guaranted.
0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.
25
CPHA
Clock Phase
Selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is
used in both master and slave mode. For successful communication between serial devices, the devices
must have identical clock phase settings. In Continuous SCK mode, the bit value is ignored and the
transfers are done as if the CPHA bit is set to 1.
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
24
LSBFE
LSB First
Specifies whether the LSB or MSB of the frame is transferred first.
0 Data is transferred MSB first.
1 Data is transferred LSB first.
23–22
PCSSCK
PCS to SCK Delay Prescaler
Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK. See the
CSSCK field description for information on how to compute the PCS to SCK Delay. Refer
PCS to SCK
Delay (t
CSC
) for more details.
Table continues on the next page...
Chapter 45 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1137