NXP Semiconductors K22F series, Reference Manual, Page: 1065 / 1407

42.3.1.2 Software reset
Writing 1 to CR[SWR] forces the equivalent of a VBAT POR to the rest of the RTC
module. CR[SWR] is not affected by the software reset and must be cleared by software.
The access control registers are not affected by either VBAT POR or the software reset;
they are reset by the chip reset.
42.3.1.3 Supervisor access
When the supervisor access control bit is clear, only supervisor mode software can write
to the RTC registers, non-supervisor mode software will generate a bus error. Both
supervisor and non-supervisor mode software can always read the RTC registers.
42.3.2 Time counter
The time counter consists of a 32-bit seconds counter that increments once every second
and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle.
Reading the time counter (either seconds or prescaler) while it is incrementing may return
invalid data due to synchronization of the read data bus. If it is necessary for software to
read the prescaler or seconds counter when they could be incrementing, it is
recommended that two read accesses are performed and that software verifies that the
same data was returned for both reads.
The time seconds register and time prescaler register can be written only when SR[TCE]
is clear. Always write to the prescaler register before writing to the seconds register,
because the seconds register increments on the falling edge of bit 14 of the prescaler
register.
The time prescaler register increments provided SR[TCE] is set, SR[TIF] is clear,
SR[TOF] is clear, and the 32.768 kHz clock source is present. After enabling the
oscillator, wait the oscillator startup time before setting SR[TCE] to allow time for the
oscillator clock output to stabilize.
If the time seconds register overflows then the SR[TOF] will set and the time prescaler
register will stop incrementing. Clear SR[TOF] by initializing the time seconds register.
The time seconds register and time prescaler register read as zero whenever SR[TOF] is
set.
SR[TIF] is set on VBAT POR and software reset and is cleared by initializing the time
seconds register. The time seconds register and time prescaler register read as zero
whenever SR[TIF] is set.
Chapter 42 Real Time Clock (RTC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1065