NXP Semiconductors K22F series, Reference Manual, Page: 1022 / 1407

Table 39-17. Conditions for loads occurring at the next enabled loading point (continued)
When a new value was written Then
To the CNTIN register and CNTINC = 1 The CNTIN register is updated with its write buffer value.
To the C(n)V register and SYNCENm = 1 – where m indicates
the pair channels (n) and (n+1) The C(n)V register is updated with its write buffer value.
To the C(n+1)V register and SYNCENm = 1 – where m
indicates the pair channels (n) and (n+1) The C(n+1)V register is updated with its write buffer value.
NOTE
• If ELSjB and ELSjA bits are different from zero, then the
channel (j) output signal is generated according to the
configured output mode. If ELSjB and ELSjA bits are zero,
then the generated signal is not available on channel (j)
output.
• If CHjIE = 1, then the channel (j) interrupt is generated
when the channel (j) match occurs.
• At the intermediate load neither the channels outputs nor
the FTM counter are changed. Software must set the
intermediate load at a safe point in time.
39.4.28 Global time base (GTB)
The global time base (GTB) is a FTM function that allows the synchronization of
multiple FTM modules on a chip. The following figure shows an example of the GTB
feature used to synchronize two FTM modules. In this case, the FTM A and B channels
can behave as if just one FTM module was used, that is, a global time base.
GTBEOUT bit
gtb_in
gtb_out
gtb_in
example glue logic
FTM module B FTM module A
GTBEEN bit
FTM counter
enable logic
FTM counter
enable
gtb_out
Figure 39-97. Global time base (GTB) block diagram
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1022 NXP Semiconductors