ERR009858
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
84
NXP Semiconductors
Description:
When parity is implemented and enabled in the PL310 Level-2 Cache Controller, for each read
from the Data RAM, parity of the read data DATARD[255:0] is compared with stored parity bits
in dedicated RAMs present on DATAPRD[31:0]. If the comparison does not match, the error is
reported using an interrupt mechanism consisting of dedicated registers (Raw and Masked
Interrupt registers).
This erratum occurs when the following conditions exist:
1) Parity is enabled (bit[21] of the Auxiliary Control Register is set to 1)
2) Read access latency on Data RAM is programmed with a value > 0x0 (bits [6:4] of the Data
RAM Latency
Register)
When the conditions above are met, parity checking between DATARD and DATAPRD occurs
during a two cycle window, including one cycle earlier than expected. If, in the early cycle,
DATARD and DATAPRD are not stable yet, parity comparison might fail. In this case, an error is
reported by the Interrupt registers, where no actual error exists.
Projected Impact:
Because of this erratum, false data parity errors might be reported by the PL310 Level-2 Cache
Controller and can cause system instability.
Workarounds:
The following software workarounds can be used to avoid this erratum:
1) Disable parity by setting bit [21] of the Auxiliary Control Register to 0 (this is the default
condition).
2) Program the read access latency of the Data RAM to the minimum value acceptable for the
implementation plus one (bits [6:4] of the Data RAM Latency Control Register). Note that this
workaround can affect performance.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used.The Freescale Linux BSP does not enable this Parity
feature and is disabled by default in all BSP releases. The BSP also ignores any assertion on the
PARITYFAIL [7:6] bits by masking the ARM-GIC parity interrupt 125. Please note that the i.MX6
does not support the parity feature (disabled by default) and hence should not be enabled by users.
ERR009858
ARM/PL310: 796171 When data banking is implemented, data parity
errors can be incorrectly generated
