ERR005185
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
57
Description:
On Cortex-A9, when a cacheable read receives an external abort, the aborted line is allocated as
invalid in the Data Cache, and any allocation in the Data Cache clears the internal exclusive
monitor.
So, if a program executes a LDREX/STREX loop which keeps on receiving an abort answer in the
middle of the LDREX/STREX sequence, then the LDREX/STREX sequence never succeeds,
leading to a possible processor livelock.
As an example, the following code sequence might exhibit the erratum:
loop LDREX
...
DSB
STREX
CMP
BNE loop
....
LDR (into aborting region)
The LDREX/STREX does not succeed on the first pass of the loop, and the BNE is mispredicted,
so, the LDR afterwards is speculatively executed.
So, the processor keeps on executing:
LDR to aborting region (this speculative LDR now appears “before” the LDREX and DSB)
LDREX
DSB
STREX
The LDR misses in L1, and never gets allocated as valid because it is aborting
The LDREX is executed, and sets the exclusive monitor
The DSB is executed. It waits for the LDR to complete, which aborts, causing an allocation (as
invalid) in the Data Cache, which clears the exclusive monitor
The STREX is executed, but the exclusive monitor is now cleared, so the STREX fails
The BNE might be mispredicted again, so the LDR is speculatively executed again, and the code
loops back on the same failing LDREX/STREX sequence.
Conditions:
The erratum happens in systems which might generate external aborts in answer to cacheable
memory requests.
ERR005185
ARM/MP: 771225—Speculative cacheable reads to aborting memory
region clear the internal exclusive monitor, may lead to livelock
