ERR008990
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
211
Description:
In I2S mode, with one FIFO in use, data is in the format left channel, right channel, left channel,
right channel. If an under-run occurs, then the left and right channels will transmit the same
previous data until new data is written to the FIFO. If the new data is valid as the right channel
starts to transmit, a channel swap occurs. Likewise when receiving data, if an overrun occurs and
the FIFO is emptied as the right channel data is being received, a channel swap occurs.
Projected Impact:
When using SSI in I2S mode, operation is limited to two-channel mode.
Workarounds:
Use SSI in two-channel mode (TCH_EN = 1) with two FIFOs enabled (TFEN1=1, TFEN0=1).
With two FIFOs in use, left channel transmit data is from FIFO0, right channel transmit data is
from FIFO1. When an under-run occurs, the left channel will transmit the previous data in FIFO0,
while the right channel will transmit the previous data in FIFO1. When new data is written into
FIFO0/FIFO1, the left channel data is always from FIFO0, and right channel data is always from
FIFO1, preventing channel swapping from occurring. Likewise when receiving data, left channel
data is always stored in FIFO0 and right channel data is always stored in FIFO1.
Proposed Solution:
No fix scheduled.
Linux BSP Status:
Software workaround integrated in Linux BSP codebase starting in release imx_3.10.53_1.1.0_ga.
ERR008990
SSI: Channel swap in single FIFO mode when an underrun or overrun
occurs
