FXTH870xD
Sensors
Freescale Semiconductor, Inc.
75
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to
get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration
bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior.
9.4.7
Timer Channel Value Registers (TPM1C1VH:TPM1C1VL)
These read/write registers contain the captured TPM1 counter value of the input capture function or the output compare value
for the output compare or PWM functions. The channel value registers are cleared by reset.
In input capture mode, reading either byte (TPM1C1VH or TPM1C1VL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPM1C1SC
register is written.
In output compare or PWM modes, writing to either byte (TPM1C1VH or TPM1C1VL) latches the value into a buffer. When both
bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPM1C1SC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.
9.5
Functional Description
All TPM1 functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor.
A 16-bit modulo register also is associated with the main 16-bit counter in the TPM1. Each TPM1 channel is optionally associated
with an MCU pin and a maskable interrupt function.
The TPM1 has center-aligned PWM capabilities controlled by the CPWMS control bit in TPM1SC. When CPWMS is set to 1,
timer counter TPM1CNT changes to an up-/down-counter and all channels in the associated TPM1 act as center-aligned PWM
channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or
buffered edge-aligned PWM mode.
The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare,
edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating
mode, these topics are covered in the associated mode sections.
9.5.1
Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section discusses selection of the clock
source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM1 is inactive. Normally, CLKSB:CLKSA
would be set to 0:1 so the bus clock drives the timer counter. The clock source for the TPM1 can be selected to be off, the bus
1
XX
10
Center-aligned
PWM
High-true pulses (clear output on compare-up)
X1
Low-true pulses (set output on compare-up)
$0019
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 52. Timer
Channel 1 Value Register High (TPM1C1VH)
$001A
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 53. Timer
Channel 1 Value Register Low (TPM1C1VL)
Table 52. Mode, Edge, and Level Selection (continued)
CPWMS
MS1B:MS1A
ELS1B:ELS1A
Mode
Configuration
Summary of Contents for FXTH870 D Series
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