FXTH870xD
Sensors
112
Freescale Semiconductor, Inc.
The external crystal connected to the X0 and XI pins provides the carrier frequency as well as the data rate clock needed for the
data rates associated with the OOK or FSK modulation. Therefore the tolerance on the data rate will depend on the
characteristics of the external crystal.
Once the data buffer is emptied the data transfer stops; the RF output stage is turned off; and the SEND control bit is cleared and
an interrupt of the MCU may be generated to wake it from the STOP1 mode. The user can test that the transmission has
completed by reading back the state of the SEND control bit or the RFIF status bit.
There is also the option to send the same data frame from 1 to 16 times with interlaced time intervals when the RF transmitter
PA output stage is off. If multiple frames of data are to be transmitted within a datagram the spacing before the first frame and
between subsequent frames can be controlled by the RFM state machine in several ways:
1.
Use of a programmable timer (random, base time, time adder).
2.
No time delays.
In addition, the RFM crystal oscillator, VCO and PLL can be turned off during any interframe timing by use of the IFPD bit.
When using the data buffer mode the user’s software should not change any bits in the RFM registers after the SEND has been
set and the transmission is still in progress. Changing RFM register contents during a transmission can lead to data faults or
errors.
13.1.2
MCU Direct Mode
When the CODE[1:0] bits are both set the encoding is controlled directly by the MCU where the data to the RF output depends
on the state of the DATA bit and the selected modulation scheme. In this mode the user software must control the RF output stage
to power up (using the SEND control bit), WAIT for the RF output stage to stabilize (monitor the RCTS status bit) and clock the
DATA to the RF output stage. In this mode the data rate and its stability will depend on the internal HFO oscillator.
Any transfers of data from the MCU will use the DATA bit which will be reflected as modulated data on the RF pin once the RF
output stage is set up to transmit. The maximum data rate in this mode will depend on the complexity of the user software and
the MCU clock rate.
The POL bit in this case simply inverts the state of the DATA bit before it drives the RF output stage.
The accuracy of the data rate in the MCU direct mode is directly dependant on the HFO accuracy.
13.2
RF Output Buffer Data Frame
When using the RF data buffer mode each frame of data is sent as 2 to 256 bits per frame with a possible two trailing bits for an
end-of-message, EOM, as shown in
Figure 90
. The actual data being transmitted in a given data frame and any combinations of
data frames into a single datagram is dependent on the user software.
The number of frames sent in a given datagram can be from 1 to 16 based on the FNUM[3:0] bits in the RFCR3. The 256-bit
buffer is divided into two pages of 128 bits as selected by the RPAGE bit in the RFCR2.
The data buffer is unloaded to the RF output starting with the least significant bit (RFD0) in the least significant byte (RFB0) up
through the most significant bit (RFD127) in the most significant byte (RFB15). This is often referred to as “little-endian” data
ordering.
Summary of Contents for FXTH870 D Series
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