NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Development Support
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 21-1
Chapter 21
Development Support
21.1 Features
Features of the Background Debug Controller (BDC) include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• Active background mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from stop or wait modes
• One hardware address breakpoint built into BDC
• Oscillator runs in Stop Mode, if BDC enabled
• COP watchdog disabled while in Active Background Mode
Features of the debug module (DBG) include:
• Two trigger comparators:
— Two a read/write (R/W) or
— One full a data + R/W
• Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
• Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
• Nine trigger modes:
— A-only
— A OR B
— A then B
— A AND B data (full mode)
— A AND NOT B data (full mode)
— Event-only B (store data)
— A then event-only B (store data)
— Inside range (A
≤
address
≤
B)
— Outside range (address < A or address > B)