NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 12-1
Chapter 12
MCU Resets, Interrupts, and System Configuration
12.1 Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the HCS08. Some interrupt sources from peripheral modules are covered in greater detail within other
sections of this data manual. This section gathers basic information about all reset and interrupt sources in
one place for easy reference. A few reset and interrupt sources, including the computer operating properly
(COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral systems with their own
sections but are part of the system control logic.
12.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation:
— Power-on detection (POR)
— Low voltage detection (LVD) with enable
— External RESET pin with enable
— COP watchdog with enable and two timeout choices
— Illegal opcode
• Illegal address access
— Serial command from a background debug host
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vectors for each module (reduces polling overhead) (see Table 12-1 )
• Software interrupt instruction (SWI)
• IRQ pin with enable, choice of polarity, level, and/or edge
• Low-voltage detect interrupt with enable
• Three timer interrupts; overflow and two channels from TPM
• Analog comparator interrupt with enable
• Carrier modulator timer interrupt with enable
• Two interrupts from keyboard interrupt with enable
• Real time interrupt with enable, available in stop2 and stop3 with multiple rates based on a separate
1-kHz self-clocked source