NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Modem Interrupt Description
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 8-3
8.1.2 Output Pin IRQ
The IRQ signal is an open drain output that is asserted low when an interrupt request is pending. The signal
is released to high by reading the IRQ_Status register via an SPI transaction. IRQ is an open drain output
that requires a passive pullup and it also can be programmed for drive strength.
8.1.2.1 Programming IRQ Pullup
A passive pullup is required on IRQ and may be done via two methods:
1. Use the onboard (nominal 40 Kohm) pullup resistor - Set irqb_pup_en bit, GPIO_Data_Out
Register 0C, Bit 7, to activate. This is the default mode.
2. Use an external resistor (value should be greater than 4 kilohms).
8.1.2.2 Setting IRQ Output Drive Strength
IRQ output drive strength is programmed by writing to irqb_drv[1:0], GPIO_Data_Out Register 0C. There
are 4 levels of drive strength with field value 00 for lowest and value 11 for greatest. The default value is
11.
NOTE
It is suggested the user leave IRQ at greatest drive strength for best
performance.
8.2 PLL_lock_irq Status Bit and Operation
As described in Section 5.28, “IRQ_Status - Register 24” , pll_lock_irq status bit indicates the LO1 PLL
has come out of lock during a TX, RX, or CCA (ED) transceiver operation. If the LO1 unlocks during the
transceiver operation, the device returns to Idle mode, and the pll_lock_irq status bit gets set as expected.
The application software must read the IRQ_Status Register 24 (clearing the pll_lock_irq status bit) before
10 tmr1_irq tmr1_mask Tmr_cmp1 match has been made. Read IRQ_Status Reg or
set tmr_cmp1_dis bit
11 tmr2_irq tmr2_mask Tmr_cmp2 or tc2_prime match has been made.
(Not functional when Tmr_cmp2 is used to exit
Doze Mode)
Read IRQ_Status Reg or
set tmr_cmp2_dis bit
12 tmr3_irq tmr3_mask Tmr_cmp3 match has been made. Read IRQ_Status Reg or
set tmr_cmp3_dis bit
13 tmr4_irq tmr4_mask Tmr_cmp4 match has been made. Read IRQ_Status Reg or
set tmr_cmp4_dis bit
1
Although some status bits can be cleared by other means, reading IRQ_Status register will always clear all status bits.
2
If a pll_lock_irq status is set, the status must be cleared before a subsequent CCA, RX or TX operation is allowed (the
requested operation will immediately abort).
Table 8-1. Modem Interrupt Sources (continued)
Item Status Bit Mask Bit Source Description
Interrupt Clear
Mechanism
1