Fast Ethernet Controller (FEC)
Freescale Semiconductor
16-7
MCF51CN128 Reference Manual, Rev. 6
Offset: 0x004
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
HB
ERR
BABR BABT GRA
TXF
TXB
RXF
RXB
MII
EB
ERR
LC
RL
UN
0
0
0
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-2. Ethernet Interrupt Event
Register (EIR)
Table 16-3. EIR Field Descriptions
Field
Description
31
HBERR
Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window
following a transmission.
30
BABR
Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
29
BABT
Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition
is caused by a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur.
28
GRA
Graceful stop complete. Indicates the graceful stop is complete. During graceful stop the transmitter is placed into a
pause state after completion of the frame currently being transmitted. This bit is set by one of three conditions:
1) A graceful stop initiated by the setting of the TCR[GTS] bit is now complete.
2) A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
3) A graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. Refer
to
Section 16.5.11, “Full Duplex Flow Control.”
27
TXF
Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has
been updated.
26
TXB
Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated.
25
RXF
Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been
updated.
24
RXB
Receive buffer interrupt. Indicates a receive buffer descriptor not the last in the frame has been updated.
23
MII
MII interrupt. Indicates the MII has completed the data transfer requested.
22
EBERR
Ethernet bus error. Indicates a system bus error occurred when a DMA transaction is underway. When the EBERR
bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC. When this occurs, software needs to
ensure that the FIFO controller and DMA also soft reset.
21
LC
Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame
truncates with a bad CRC and the remainder of the frame is discarded.
