Fast Ethernet Controller (FEC)
Freescale Semiconductor
16-3
MCF51CN128 Reference Manual, Rev. 6
You control the FEC by writing into control registers located in each block. The CSR (control and status
registers) block provides global control (Ethernet reset and enable) and interrupt managing registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and
FEC_MDIO (management data input/output) lines of the MII interface.
The FEC DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data
and receive descriptor accesses to run independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
16.1.3
Features
The FEC incorporates the following features:
•
Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
•
IEEE 802.3 full duplex flow control
•
Programmable max frame length supports IEEE 802.1 VLAN tags and priority
•
Support for full-duplex operation (200 Mbps throughput) with a minimum internal bus clock rate
of 50 MHz
•
Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate
of 50 MHz
•
Retransmission from transmit FIFO following a collision (no processor bus utilization)
•
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)
•
Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
16.2
Modes of Operation
The primary operational modes are described in this section.
