Rapid GPIO (RGPIO)
Freescale Semiconductor
10-5
MCF51CN128 Reference Manual, Rev. 6
10.3.1
RGPIO Data Direction (RGPIO_DIR)
The read/write RGPIO_DIR register defines whether a properly-enabled RGPIO pin is configured as an
input or output:
•
Setting any bit in RGPIO_DIR configures a properly-enabled RGPIO port pin as an output
•
Clearing any bit in RGPIO_DIR configures a properly-enabled RGPIO port pin as an input
At reset, all bits in the RGPIO_DIR are cleared.
Figure 10-2. RGPIO Data Direction Register (RGPIO_DIR)
10.3.2
RGPIO Data (RGPIO_DATA)
The RGPIO_DATA register specifies the write data for a properly-enabled RGPIO output pin or the
sampled read data value for a properly-enabled input pin. An attempted read of the RGPIO_DATA register
returns undefined data for disabled pins, since the data value is dependent on the device-level pin muxing
and pad implementation. The RGPIO_DATA register is read/write. At reset, all bits in the RGPIO_DATA
registers are cleared.
To set bits in a RGPIO_DATA register, directly set the RGPIO_DATA bits or set the corresponding bits in
the RGPIO_SET register. To clear bits in the RGPIO_DATA register, directly clear the RGPIO_DATA
bits, or clear the corresponding bits in the RGPIO_CLR register. Setting a bit in the RGPIO_TOG register
inverts (toggles) the state of the corresponding bit in the RGPIO_DATA register.
Offset: RGPI 0x0 (RGPIO_DIR)
RGPI 0x8
RGPI 0xC
Access: Read/write
Read-only
Read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
DIR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 10-5. RGPIO_DIR Field Descriptions
Field
Description
15–0
DIR
Data direction.
0 A properly-enabled RGPIO pin is configured as an input
1 A properly-enabled RGPIO pin is configured as an output
