Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-4
Freescale Semiconductor
interrupted. After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer
from the exception vector table using the vector number as the offset, and then jumps to that address to
begin execution of the service routine. After the status register is stored in the exception stack frame, the
SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and
all lower values while in the service routine.
All ColdFire processors guarantee that the first instruction of the service routine is executed before
interrupt sampling is resumed. By making this initial instruction a load of the SR, interrupts can be safely
disabled, if required. Optionally, the processor can be configured to automatically raise the mask level to
7 for any interrupt during exception processing by setting CPUCR[IME].
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the
ColdFire Programmer’s Reference Manual
. For
additional information specific to this device, see
Chapter 8, “Interrupt Controller (CF1_INTC)
.”
5.4.1
RESET/PTC3
On the MCF51CN128 devices, RESET is multiplexed with PTC3. This pin is open drain, and is also used
during factory test for applying high voltages required for flash test purposes. Because of this, the
RESET/PTC3 pin is subject to the following restrictions:
1. This pin does not contain a clamp diode to V
DD
and must not be driven above V
DD
.
2. The voltage measured on the internally pulled up RESET pin is not pulled to V
DD
. The internal
gates connected to this pin are pulled to V
DD
. The RESET pull-up must not be used to pull-up
components external to the microcontroller.
3. On the MCF51CN128, RESET co-exists on PTC3. RESET is the default function upon power up.
To avoid startup problems, PTC3 must only be programmed as an output function when used as
GPIO.
4. Asserting a low on RESET/PTC3, can wake the device from STOP2 mode, assuming that the pin
is left programmed as RESET.
5.4.2
External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the
microcontroller is in stop mode and system clocks are shut down, a separate asynchronous path is used, so
the IRQ pin (if enabled) can wake the microcontroller.
5.4.2.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be set for the IRQ pin to act as the interrupt request
(IRQ) input. As an IRQ input, you can choose the polarity of edges or levels detected (IRQEDG), whether
the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an interrupt or
only sets the IRQF flag which can be polled by software (IRQIE).
