Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
5-3
The processor generates a reset in response to any of these events if CPUCR[IRD] is cleared. If this
configuration bit is set, the processor generates the appropriate exception instead of forcing a reset.
5.3.3
Illegal Address Detect (ILAD)
By default the V1 ColdFire core enables the generation of an MCU reset in response to any
processor-detected address error, bus error termination, RTE format error or fault-on-fault condition.
The processor generates a reset if CPUCR[ARD] is cleared. If this configuration bit is set, the processor
generates the appropriate exception instead of forcing a reset, or simply halts the processor in response to
the fault-on-fault condition.
5.4
Interrupts & Exceptions
The interrupt architecture of ColdFire utilizes a 3-bit encoded interrupt priority level sent from the
interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest
priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt
requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask
value (I) contained in bits 10:8 of the processor’s status register (SR). If the priority level is greater than
the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates
interrupt exception processing.
Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6
are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct
operation, the ColdFire processor requires that, once asserted, the interrupt source remain asserted until
explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU does the following tasks in order:
1. enters supervisor mode,
2. disables trace mode,
3. uses the vector provided by the INTC when the interrupt was signaled (if CPUCR[IAE] is cleared)
or explicitly fetches an 8-bit vector from the INTC (if CPUCR[IAE] is set).
This byte-sized operand fetch during exception processing is known as the interrupt acknowledge (IACK)
cycle. The fetched data provides an index into the exception vector table which contains up to 256
addresses (depending upon the specific device), each pointing to the beginning of a specific exception
service routine.
In particular, the first 64 exception vectors are reserved for the processor to handle reset, error conditions
(access, address), arithmetic faults, system calls, etc. Vectors 64–255 are reserved for interrupt service
routines. The MCF51CN128 series microcontrollers support 36 peripheral interrupt sources and an
additional seven software interrupt sources. These are mapped into the standard seven ColdFire interrupt
levels, with up to 9 levels of prioritization within a given level by the V1 ColdFire interrupt controller. See
for details.
After the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames are two longwords in length, and contain 32 bits of
vector and status register data, along with the 32-bit program counter value of the instruction that was
