NXP Semiconductors freescale KV4 Series, Reference Manual

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FTM counter
0
3
4 0 1 2
3 4 0 1 2 3 4 0 1
2
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
channel (n) output
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
channel (n)
match
counter
overflow
FTM counting is up.
Channel (n) is in high-true EPWM mode.
PS[2:0] = 001
CNTIN = 0x0000
MOD = 0x0004
CnV = 0x0002
prescaler counter
Figure 39-167. Notation used
39.5.1 Clock source
The FTM has only one clock domain: the system clock.
39.5.1.1 Counter clock source
The CLKS[1:0] bits in the SC register select one of three possible clock sources for the
FTM counter or disable the FTM counter. After any MCU reset, CLKS[1:0] = 0:0 so no
clock source is selected.
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
The fixed frequency clock is an alternative clock source for the FTM counter that allows
the selection of a clock other than the system clock or an external clock. This clock input
is defined by chip integration. Refer to the chip specific documentation for further
information.
The external clock passes through a synchronizer clocked by the system clock to assure
that counter transitions are properly aligned to system clock transitions.Therefore, to
meet Nyquist criteria considering also jitter, the frequency of the external clock source
must not exceed 1/4 of the system clock frequency.
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
948
Preliminary
Freescale Semiconductor, Inc.