NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 942 / 1359

FTMx_SYNCONF field descriptions (continued)
Field Description
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
SWOC
SWOCTRL Register Synchronization
0 SWOCTRL register is updated with its buffer value at all rising edges of system clock.
1 SWOCTRL register is updated with its buffer value by the PWM synchronization.
4
INVC
INVCTRL Register Synchronization
0 INVCTRL register is updated with its buffer value at all rising edges of system clock.
1 INVCTRL register is updated with its buffer value by the PWM synchronization.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
CNTINC
CNTIN Register Synchronization
0 CNTIN register is updated with its buffer value at all rising edges of system clock.
1 CNTIN register is updated with its buffer value by the PWM synchronization.
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
HWTRIGMODE
Hardware Trigger Mode
0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
39.4.25 FTM Inverting Control (FTMx_INVCTRL)
This register controls when the channel (n) output becomes the channel (n+1) output, and
channel (n+1) output becomes the channel (n) output. Each INVmEN bit enables the
inverting operation for the corresponding pair channels m.
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register
synchronization.
Address: Base a 90h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
KV4x Reference Manual, Rev. 2, 02/2015
942
Preliminary
Freescale Semiconductor, Inc.