NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 910 / 1359

39.4.7 Channel (n) Value (FTMx_CnV)
These registers contain the captured FTM counter value for the input modes or the match
value for the output modes.
In Input Capture, Capture Test, and Dual Edge Capture modes, any write to a CnV
register is ignored.
In output modes, writing to a CnV register latches the value into a buffer. A CnV register
is updated with the value of its write buffer according to
Registers updated from write
buffers .
If FTMEN = 0, this write coherency mechanism may be manually reset by writing to the
CnSC register whether BDM mode is active or not.
Address: Base a 10h (8d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CnV field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
VAL Channel Value
Captured FTM counter value of the input modes or the match value for the output modes
39.4.8 Counter Initial Value (FTMx_CNTIN)
The Counter Initial Value register contains the initial value for the FTM counter.
Writing to the CNTIN register latches the value into a buffer. The CNTIN register is
updated with the value of its write buffer according to
Registers updated from write
buffers .
When the FTM clock is initially selected, by writing a non-zero value to the CLKS bits,
the FTM counter starts with the value 0x0000. To avoid this behavior, before the first
write to select the FTM clock, write the new value to the the CNTIN register and then
initialize the FTM counter by writing any value to the CNT register.
Memory map and register definition
KV4x Reference Manual, Rev. 2, 02/2015
910
Preliminary
Freescale Semiconductor, Inc.