NXP Semiconductors freescale KV4 Series, Reference Manual

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PDBx_CHnS field descriptions (continued)
Field Description
one of the pre-triggers from PDB channel n , is in progress, new trigger from PDB channel's
corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0’s to clear the
sequence error flags.
38.4.7 Channel n Delay 0 register (PDBx_CHnDLY0)
Address: Base a 18h (40d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY0 field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DLY PDB Channel Delay
Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the
counter is equal to DLY. Reading this field returns the value of internal register that is effective for the
current PDB cycle.
38.4.8 Channel n Delay 1 register (PDBx_CHnDLY1)
Address: Base a 1Ch (40d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY1 field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DLY PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
Memory map and register definition
KV4x Reference Manual, Rev. 2, 02/2015
878
Preliminary
Freescale Semiconductor, Inc.