NXP Semiconductors freescale KV4 Series, Reference Manual

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38.2.1 Features
• Up to 15 trigger input sources and one software trigger source
• Up to 8 configurable PDB channels for ADC hardware trigger
• One PDB channel is associated with one ADC
• One trigger output for ADC hardware trigger and up to 8 pre-trigger outputs for
ADC trigger select per PDB channel
• Trigger outputs can be enabled or disabled independently
• One 16-bit delay register per pre-trigger output
• Optional bypass of the delay registers of the pre-trigger outputs
• Operation in One-Shot or Continuous modes
• Optional back-to-back mode operation, which enables the ADC conversions
complete to trigger the next PDB channel
• One programmable delay interrupt
• One sequence error interrupt
• One channel flag and one sequence error flag per pre-trigger
• DMA support
• Up to 8 DAC interval triggers
• One interval trigger output per DAC
• One 16-bit delay interval register per DAC trigger output
• Optional bypass of the delay interval trigger registers
• Optional external triggers
• Up to 8 pulse outputs (pulse-out's)
• Pulse-out's can be enabled or disabled independently
• Programmable pulse width
NOTE
The number of PDB input and output triggers are chip-specific.
See the chip-specific PDB information for details.
Chapter 38 Programmable Delay Block (PDB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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