NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 849 / 1359

OCTRL[POLA] and OCTRL[POLB] before enabling the output pins. A fault condition
can result in the PWM output being tristated, forced to a logic 1, or forced to a logic 0
depending on the values programmed into the OCTRL[PWMxFS] fields.
1
0
PWM23
POLA
PWMAFS[1]
PWM_A output
PWM_A_EN
1
0
PWM45
PWMBFS[1]
PWM_B output
PWM_B_EN
MASKA
MASKB
POLB
PWMAFS[0]
PWMBFS[0]
Disable
PWM_A
PWM_B
Disable
from Deadtime
logic
Fractional
Delay 2-3
Fractional
Delay 4-5
PWM_X
double pulse
output option
Figure 37-245. Output Logic
37.5.2.11 E-Capture
Commensurate with the idea of controlling both edges of an output signal, the Enhanced
Capture (E-Capture) logic is designed to measure both edges of an input signal. As a
result, when a submodule pin is configured for input capture, the CVALx registers
associated with that pin are used to record the edge values.
The following figure is a block diagram of the E-Capture circuit. Upon entering the pin
input, the signal is split into two paths. One goes straight to a mux input where software
can select to pass the signal directly to the capture logic for processing. The other path
connects the signal to an 8 bit counter which counts both the rising and falling edges of
the signal. The output of this counter is compared to an 8 bit value that is specified by the
user (EDGCMPx) and when the two values are equal, the comparator generates a pulse
that resets the counter. This pulse is also supplied to the mux input where software can
select it to be processed by the capture logic. This feature permits the E-Capture circuit to
count up to 256 edge events before initiating a capture event. this feature is useful for
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
849