NXP Semiconductors freescale KV4 Series, Reference Manual

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FMC_PFB0CR field descriptions (continued)
Field Description
These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is
written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents
are cleared. This field always reads as zero.
Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System
software is required to maintain memory coherency when any segment of the flash memory is
programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is
completed and before the new memory image is accessed.
The bit setting definitions are for each bit in the field.
0 No cache way invalidation for the corresponding cache
1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
19
S_B_INV
Invalidate Prefetch Speculation Buffer
This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be
invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are
immediately cleared. This bit always reads as zero.
0 Speculation buffer and single entry buffer are not affected.
1 Invalidate (clear) speculation buffer and single entry buffer.
18–17
B0MW[1:0]
Bank 0 Memory Width
This read-only field defines the width of the bank 0 memory.
00 32 bits
01 64 bits
10 128 bits
11 Reserved
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–5
CRC[2:0]
Cache Replacement Control
This 3-bit field defines the replacement algorithm for accesses that are cached.
000 LRU replacement algorithm per set across all four ways
001 Reserved
010 Independent LRU with ways [0-1] for ifetches, [2-3] for data
011 Independent LRU with ways [0-2] for ifetches, [3] for data
1xx Reserved
4
B0DCE
Bank 0 Data Cache Enable
This bit controls whether data references are loaded into the cache.
0 Do not cache data references.
1 Cache data references.
3
B0ICE
Bank 0 Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
Table continues on the next page...
Chapter 31 Flash Memory Controller (FMC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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