NXP Semiconductors freescale KV4 Series, Reference Manual

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If the auto trim is being performed on the 4 MHz IRC, the calculated expected count
value must be multiplied by 128 before storing it in the ATCV register. Therefore, the
ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the
following formula.
(128)
30.5 Initialization / Application information
This section describes how to initialize and configure the MCG module in an application.
The following sections include examples on how to initialize the MCG and properly
switch between the various available modes.
30.5.1 MCG module initialization sequence
The MCG comes out of reset configured for FEI mode.
The internal reference will stabilize in t
irefsts
microseconds before the FLL can acquire
lock. As soon as the internal reference is stable, the FLL will acquire lock in t
fll_acquire
milliseconds.
30.5.1.1 Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes that can be
directly switched to upon reset are FEE, FBE, and FBI modes (see
Figure 30-13 ).
Reaching any of the other modes requires first configuring the MCG for one of these
three intermediate modes. Care must be taken to check relevant status bits in the MCG
status register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in C2 register.
2. Write to C1 register to select the clock mode.
• If entering FEE mode, set C1[FRDIV] appropriately, clear C1[IREFS] bit to
switch to the external reference, and leave C1[CLKS] at 2'b00 so that the output
of the FLL is selected as the system clock source.
Chapter 30 Multipurpose Clock Generator (MCG)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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