NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 480 / 1359

Table 25-17. Refresh for 8-bit access
WDOG_REFRESH[15:8] WDOG_REFRESH[7:0]
Sequence value1 or
value2 match
Mismatch
exception
Current Value
0xB4 0x80 Value2 match No
Write 1 0xB4 0x02 No match No
Write 2 0xA6 0x02 Value1 match No
Write 3
0xB4 0x02 No match No
Write 4
0xB4 0x80 Value2 match.
Sequence complete.
No
Write 5
0x02 0x80 No match Yes
As shown in the preceding table, the refresh register holds its reset value initially.
Thereafter, two 8-bit accesses are performed on the register to write the first value of the
refresh sequence. No mismatch exception is registered on the intermediate write, Write1.
The sequence is completed by performing two more 8-bit accesses, writing in the second
value of the sequence for a successful refresh. It must be noted that the match of value2
takes place only when the complete 16-bit value is correctly written, write4. Hence, the
requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is
checked by measuring the gap between write2 and write4.
It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock
sequence remains unchanged. The difference for 8-bit accesses is that the criterion for
detecting a mismatch is less strict. Any 16-bit access still needs to adhere to the original
guidelines, mentioned in the sections
Refreshing the Watchdog .
25.10 Restrictions on watchdog operation
This section mentions some exceptions to the watchdog operation that may not be
apparent to you.
• Restriction on unlock/refresh operations—In the period between the closure of the
WCT window after unlock and the actual reload of the watchdog timer, unlock and
refresh operations need not be attempted.
• The update and reload of the watchdog timer happens two to three watchdog clocks
after WCT window closes, following a successful configuration on unlock.
• Clock Switching Delay—The watchdog uses glitch-free multiplexers at two places –
one to choose between the LPO oscillator input and alternate clock input, and the
other to choose between the watchdog functional clock and fast clock input for
Restrictions on watchdog operation
KV4x Reference Manual, Rev. 2, 02/2015
480
Preliminary
Freescale Semiconductor, Inc.