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DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued)
Field
Description
0
The minor loop offset is not applied to the DADDR
1
The minor loop offset is applied to the DADDR
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation
and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration
count is completed, additional processing is performed.
23.3.23 TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCDn_NBYTES_MLOFFYES)
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which
register to use depends on whether minor loop mapping is disabled, enabled but not used
for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• Minor loop offset is enabled (SMLOE or DMLOE = 1)
If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then
refer to the TCD_NBYTES_MLNO register description.
Address: 4000_8000h base + 1008h (32d × i), where i=0d to 15d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
* Notes:
Chapter 23 Direct Memory Access Controller (eDMA)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
415
Summary of Contents for freescale KV4 Series
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