NXP Semiconductors freescale KV4 Series, Reference Manual

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20.1.1 Crossbar Switch Master Assignments
The masters connected to the crossbar switch are assigned as follows:
Master module Master port number
ARM core code bus 0
ARM core system bus 1
DMA 2
20.1.2 Crossbar Switch Slave Assignments
The slaves connected to the crossbar switch are assigned as follows:
Slave module Slave port number
Flash memory controller S0
SRAM controller S1
AIPS_Lite bus controller/GPIO S2
20.2 Introduction
The information found here provides information on the layout, configuration, and
programming of the crossbar switch.
The crossbar switch connects bus masters and bus slaves using a crossbar switch
structure. This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access the
same slave.
20.2.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• 32-bit data bus
Introduction
KV4x Reference Manual, Rev. 2, 02/2015
332
Preliminary
Freescale Semiconductor, Inc.