NXP Semiconductors freescale KV4 Series, Reference Manual

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SIM_SCGC4 field descriptions (continued)
Field Description
24
eFlexPWM0
eFlexPWM submodule 0 Clock Gate Control
This bit controls the clock gate to the PWM submodule 0.
0 Clock disabled
1 Clock enabled
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19
CMP
Comparators Clock Gate Control
This bit controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
18–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
UART1
UART1 Clock Gate Control
This bit controls the clock gate to the UART1 module.
0 Clock disabled
1 Clock enabled
10
UART0
UART0 Clock Gate Control
This bit controls the clock gate to the UART0 module.
0 Clock disabled
1 Clock enabled
9–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
I2C0
I2C0 Clock Gate Control
This bit controls the clock gate to the I
2
C0 module.
0 Clock disabled
1 Clock enabled
5–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
EWM
EWM Clock Gate Control
This bit controls the clock gate to the EWM module.
0 Clock disabled
1 Clock enabled
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 13 System Integration Module (SIM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
189