NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 175 / 1359

SIM_SOPT2 field descriptions
Field Description
31
NANOEDGECLK2XSEL
Nanoedge clock(PWM 2x clock) select
Selects the PLL 2x clock(MCGPLLCLK2X) or 1x clock (MCGPLLCLK) as the nanoedge clock
source.
0 MCGPLLCLK
1 MCGPLLCLK2X
30–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
TRACECLKSEL
Debug trace clock select
Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.
0 MCGOUTCLK
1 Core/system clock
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–5
CLKOUTSEL
CLKOUT select
Selects the clock to output on the CLKOUT pin.
000 Reserved
001 Reserved
010 Flash clock
011 LPO clock (1 kHz)
100 MCGIRCLK
101 OSCERCLK_UNDIV
110 OSCERCLK
111 Reserved
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 13 System Integration Module (SIM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
175