NXP Semiconductors freescale KV4 Series, Reference Manual

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Test-Logic-Reset state results in the IDCODE instruction being loaded on the falling
edge of TCK. Asynchronous entry into the Test-Logic-Reset state results in asynchronous
loading of the IDCODE instruction. During the Capture-IR TAP controller state, the
instruction shift register is loaded with the value 0001b , making this value the register's
read value when the TAP controller is sequenced into the Shift-IR state.
R
W
Reset:
Instruction Code
2 1 0
0 0 0 1
0 0 0 1
3
Figure 48-2. Instruction register
48.3.2 Bypass register
The bypass register is a single-bit shift register path selected for serial data transfer
between TDI and TDO when the BYPASS, CLAMP, HIGHZ or reserve instructions are
active. After entry into the Capture-DR state, the single-bit shift register is set to a logic
0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.
48.3.3 Device identification register
The device identification (JTAG ID) register, shown in the following figure, allows the
revision number, part number, manufacturer, and design center responsible for the design
of the part to be determined through the TAP. The device identification register is
selected for serial data transfer between TDI and TDO when the IDCODE instruction is
active. Entry into the Capture-DR state while the device identification register is selected
loads the IDCODE into the shift register to be shifted out on TDO in the Shift-DR state.
No action occurs in the Update-DR state.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Part Revision Number Design Center Part Identification Number
W
Reset PRN DC PIN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Part Identification Number Manufacturer Identity Code 1
W
Reset PIN (contd.) MIC 1
The following table describes the device identification register functions.
Chapter 48 JTAG Controller (JTAGC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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