NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1340 / 1359

48.2.1 TCK—Test clock input
Test Clock Input (TCK) is an input pin used to synchronize the test logic and control
register access through the TAP.
48.2.2 TDI—Test data input
Test Data Input (TDI) is an input pin that receives serial test instructions and data. TDI is
sampled on the rising edge of TCK.
48.2.3 TDO—Test data output
Test Data Output (TDO) is an output pin that transmits serial output for test instructions
and data. TDO is three-stateable and is actively driven only in the Shift-IR and Shift-DR
states of the TAP controller state machine, which is described in
TAP controller state
machine .
48.2.4 TMS—Test mode select
Test Mode Select (TMS) is an input pin used to sequence the IEEE 1149.1-2001 test
control state machine. TMS is sampled on the rising edge of TCK.
48.3 Register description
This section provides a detailed description of the JTAGC block registers accessible
through the TAP interface, including data registers and the instruction register. Individual
bit-level descriptions and reset states of each register are included. These registers are not
memory-mapped and can only be accessed through the TAP.
48.3.1 Instruction register
The JTAGC block uses a 4-bit instruction register as shown in the following figure. The
instruction register allows instructions to be loaded into the block to select the test to be
performed or the test data register to be accessed or both. Instructions are shifted in
through TDI while the TAP controller is in the Shift-IR state, and latched on the falling
edge of TCK in the Update-IR state. The latched instruction value can only be changed in
the Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into the
Register description
KV4x Reference Manual, Rev. 2, 02/2015
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Preliminary
Freescale Semiconductor, Inc.