NXP Semiconductors freescale KV4 Series, Reference Manual

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48.1.2 Features
The JTAGC block is compliant with the IEEE 1149.1-2001 standard, and supports the
following features:
• IEEE 1149.1-2001 Test Access Port (TAP) interface
• 4 pins (TDI, TMS, TCK, and TDO)
• Instruction register that supports several IEEE 1149.1-2001 defined instructions as
well as several public and private device-specific instructions. Refer to Table 48-3
for a list of supported instructions.
• Bypass register, boundary scan register, and device identification register.
• TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry.
48.1.3 Modes of operation
The JTAGC block uses a power-on reset indication as its primary reset signals. Several
IEEE 1149.1-2001 defined test modes are supported, as well as a bypass mode.
48.1.3.1 Reset
The JTAGC block is placed in reset when either power-on reset is asserted, or the TMS
input is held high for enough consecutive rising edges of TCK to sequence the TAP
controller state machine into the Test-Logic-Reset state. Holding TMS high for five
consecutive rising edges of TCK guarantees entry into the Test-Logic-Reset state
regardless of the current TAP controller state. Asserting power-on reset results in
asynchronous entry into the reset state. While in reset, the following actions occur:
• The TAP controller is forced into the Test-Logic-Reset state, thereby disabling the
test logic and allowing normal operation of the on-chip system logic to continue
unhindered
• The instruction register is loaded with the IDCODE instruction
Introduction
KV4x Reference Manual, Rev. 2, 02/2015
1338
Preliminary
Freescale Semiconductor, Inc.