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SPI_RSER field descriptions (continued)
Field
Description
Selects between generating a DMA request or an interrupt request. When the RFDF flag bit in the SR is
set, and the RFDF_RE bit in the RSER is set, the RFDF_DIRS bit selects between generating an interrupt
request or a DMA request.
0
Interrupt request.
1
DMA request.
15
Reserved
Always write the reset value to this field.
This field is reserved.
14
Reserved
Always write the reset value to this field.
This field is reserved.
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
44.4.7 PUSH TX FIFO Register In Master Mode (SPI_PUSHR)
Specifies data to be transferred to the TX FIFO and CMD FIFO. An 8- or 16-bit write
access to the TXDATA field transfers the 16 bits of data to the TX FIFO. A write access
to the command fields transfers the 16 bits of command information to the CMD FIFO.
In Master mode, the register transfers 16 bits of data to the TX FIFO and 16 bits of
command information to the CMD FIFO.In Slave mode, the CMD FIFO is not used and
the 16 bits of command information are reserved.
The TX FIFO and CMD FIFO must be filled simultaneously. In other words, you must
perform write accesses to both the data and command fields for every PUSHR operation.
Because both the TX FIFO and CMD FIFO are written to and read from simultaneously,
they behave as a single 32 bit FIFO.
A read access of PUSHR returns the topmost TX FIFO and CMD FIFO entries
concatenated.
When the module is disabled, writing to this register does not update the FIFO.
Therefore, any reads performed while the module is disabled return the last PUSHR write
performed while the module was still enabled.
Address: 4002_C000h base + 34h offset = 4002_C034h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 44 Serial Peripheral Interface (SPI)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1195
Summary of Contents for freescale KV4 Series
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