NXP Semiconductors freescale KV4 Series, Reference Manual

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In master mode, the CTAR registers define combinations of transfer attributes, such as
frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In
slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer
attributes.
44.1.5 TX FIFO size
Table 44-1. SPI transmit FIFO size
SPI Module Transmit FIFO size
SPI0 4
44.1.6 RX FIFO Size
SPI supports up to 16-bit frame size during reception.
Table 44-2. SPI receive FIFO size
SPI Module Receive FIFO size
SPI0 4
44.1.7 Number of PCS signals
The following table shows the number of peripheral chip select signals available per SPI
module.
Table 44-3. SPI PCS signals
SPI Module PCS Signals
SPI0 SPI_PCS[5:0]
44.1.8 SPI Operation in Low Power Modes
In VLPR and VLPW modes the SPI is functional; however, the reduced system
frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW
modes the max SPI_CLK frequency is 2MHz.
In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not
functional, but it is powered so that it retains state.
Chip-specific SPI information
KV4x Reference Manual, Rev. 2, 02/2015
1170
Preliminary
Freescale Semiconductor, Inc.