• Format B: 256 IDAFs (standard IDs or extended 14-bit ID slices including IDE and
RTR)
• Format C: 512 IDAFs (standard or extended 8-bit ID slices)
Note
A chosen format is applied to all entries of the filter table. It is
not possible to mix formats within the table.
Every frame available in the FIFO has a corresponding IDHIT (Identifier Acceptance
Filter Hit Indicator) that can read in the IDHIT field from C/S word, as shown in the Rx
FIFO Structure description. Another way the CPU can obtain this information is by
accessing the CAN_RXFIR register. The CAN_RXFIR[IDHIT] field refers to the
message at the output of the FIFO and is valid while the CAN_IFLAG1[BUF5I] flag is
asserted. The CAN_RXFIR register must be read only before clearing the flag, which
guarantees that the information refers to the correct frame within the FIFO.
Up to 16 elements of the filter table are individually affected by the Individual Mask
Registers (CAN_RXIMRx), according to the setting of CAN_CTRL2[RFFN], allowing
very powerful filtering criteria to be defined. If the CAN_MCR[IRMQ] bit is negated,
then the FIFO filter table is affected by CAN_RXFGMASK.
43.5.7.1 Rx FIFO under DMA Operation
The receive-only FIFO can support DMA, this feature is enabled by asserting both the
CAN_MCR[RFEN] and CAN_MCR[DMA] bits. The reset value of CAN_MCR[DMA]
bit is zero to maintain backward compatibility with previous versions of the module that
did not have the DMA feature.
The DMA controller can read the received message by reading a Message Buffer
structure at the FIFO output port at the 0x80-0x8C address range.
When CAN_MCR[DMA] is asserted the CPU must not access the FIFO output port
address range. Before enabling the CAN_MCR[DMA], the CPU must service the
IFLAGs asserted in the Rx FIFO region. Otherwise, these IFLAGs may show that the
FIFO has data to be serviced, and mistakenly generate a DMA request. Before disabling
the CAN_MCR[DMA], the CPU must perform a clear FIFO operation.
The CAN_IFLAG1[BUF5I] (Frames available in Rx FIFO) is asserted when there is at
least one frame available to be read from the FIFO, consequently a DMA request is
generated simultaneously. Upon receiving the request, the DMA controller can read the
message (accessing the output of the FIFO as a Message Buffer). The DMA reading
process must end by reading address 0x8C, which clears the CAN_IFLAG1[BUF5I] and
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
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Preliminary
Freescale Semiconductor, Inc.
Summary of Contents for freescale KV4 Series
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