NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1092 / 1359

CANx_MCR field descriptions (continued)
Field Description
When asserted, this bit enables the Tx abort mechanism. This mechanism guarantees a safe procedure
for aborting a pending transmission, so that no frame is sent in the CAN bus without notification. This bit
can be written only in Freeze mode because it is blocked by hardware in other modes.
NOTE: When CAN_MCR[AEN] is asserted, only the abort mechanism (see Transmission abort
mechanism ) must be used for updating Mailboxes configured for transmission.
CAUTION: Writing the Abort code into Rx Mailboxes can cause unpredictable results when the
CAN_MCR[AEN] is asserted.
0 Abort disabled.
1 Abort enabled.
11
Reserved
This field is reserved.
10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–8
IDAM
ID Acceptance Mode
This 2-bit field identifies the format of the Rx FIFO ID Filter Table elements. Note that all elements of the
table are configured at the same time by this field (they are all the same format). See Section "Rx FIFO
Structure". This field can be written only in Freeze mode because it is blocked by hardware in other
modes.
00 Format A: One full ID (standard and extended) per ID Filter Table element.
01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table
element.
10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
11 Format D: All frames rejected.
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
MAXMB Number Of The Last Message Buffer
This 7-bit field defines the number of the last Message Buffers that will take part in the matching and
arbitration processes. The reset value (0x0F) is equivalent to a 16 MB configuration. This field can be
written only in Freeze mode because it is blocked by hardware in other modes.
Number of the last MB = MAXMB
NOTE: MAXMB must be programmed with a value smaller than or equal to the number of available
Message Buffers.
Additionally, the definition of MAXMB value must take into account the region of MBs occupied by Rx
FIFO and its ID filters table space defined by RFFN bit in CAN_CTRL2 register. MAXMB also impacts the
definition of the minimum number of peripheral clocks per CAN bit as described in Table "Minimum Ratio
Between Peripheral Clock Frequency and CAN Bit Rate" (see
Arbitration and matching timing ).
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
1092
Preliminary
Freescale Semiconductor, Inc.