NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1065 / 1359

Table 42-1. Modes of operation (continued)
Modes Description
Low-Leakage
The LPTMR continues to operate normally and
may be configured to exit the low-power mode
by generating an interrupt request.
Debug
The LPTMR operates normally in Pulse Counter
mode, but counter does not increment in Time
Counter mode.
42.3 LPTMR signal descriptions
Table 42-2. LPTMR signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input pin
42.3.1 Detailed signal descriptions
Table 42-3. LPTMR interface—detailed signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Timing Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
42.4 Memory map and register definition
LPTMR memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_0000 Low Power Timer Control Status Register (LPTMR_CSR) 32 R/W 0000_0000h 42.4.1/1066
Table continues on the next page...
Chapter 42 Low-Power Timer (LPTMR)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1065