NXP Semiconductors freescale KV4 Series, Reference Manual

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When any of the counter registers is read, the contents of each counter register is written
to the corresponding hold register. Taking a snapshot of the counters' values provides a
consistent view of a system position and a velocity to be attained. The POSMATCH
output can be used in conjunction with a timer channel to capture a time stamp of when
these registers are read.
The position counter is 32 bits wide. To ensure it can be reliably initialized with two 16-
bit accesses, two registers, an upper and a lower initialization register, are provided. The
upper initialization register (UINIT) and lower initialization register (LINIT) should be
modified with the desired value. Next, the position counter can be loaded by writing 1 to
CTRL[SWIP]. Alternatively, either CTRL[XIP] or CTRL[HIP] can enable the position
counter to be initialized in response to a HOME or INDEX signal transition.
41.6 Resets
There are no special requirements. This module is reset by any system reset.
41.7 Clocks
The IPBus clock is the only clock required by this module in normal operation.
41.8 Interrupts
The following table lists the module interrupts.
Table 41-23. Interrupt Summary
Core Interrupt Interrupt Flag Interrupt Enable Description
ipi_int_home CTRL[HIRQ] CTRL[HIE] HOME signal transition interrupt
ipi_int_index
CTRL[XIRQ] CTRL[XIE]
INDEX signal transition interrupt or roll-over/
under interrupt
CTRL2[ROIRQ] CTRL2[ROIE]
CTRL2[RUIRQ] CTRL2[RUIE]
ipi_int_wdog CTRL[DIRQ] CTRL[DIE] Watchdog timeout interrupt
ipi_int_comp CTRL[CMPIRQ] CTRL[CMPIE] Compare match interrupt
ipi_int_sab CTRL2[SABIRQ] CTRL2[SABIE]
Simultaneous PHASEA and PHASEB change
interrupt
Resets
KV4x Reference Manual, Rev. 2, 02/2015
1062
Preliminary
Freescale Semiconductor, Inc.