NXP Semiconductors freescale KV4 Series, Reference Manual

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Chapter 40
Periodic Interrupt Timer (PIT)
Chip-specific PIT information
40.1.1 PIT/DMA Periodic Trigger Assignments
The PIT generates periodic trigger events to the DMA Mux as shown in the table below.
Table 40-1. PIT channel assignments for periodic DMA triggering
DMA Channel Number PIT Channel
DMA Channel 0 PIT Channel 0
DMA Channel 1 PIT Channel 1
DMA Channel 2 PIT Channel 2
DMA Channel 3 PIT Channel 3
40.1.2 PIT Trigger Output Assignments
The PIT timer channels are used to trigger other peripheral events such as ADC
acquisitions or DMA transfers. On this device the following assignments have been made
for each of the PIT channels.
PIT channel 0 output - XBARA_IN42, XBARB_IN24
PIT channel 1 output - XBARA_IN43 , XBARB_IN25
PIT channel 2 output - XBARA_IN50
PIT channel 3 output - XBARA_IN51
Routing the PIT channel outputs via XBARA/B provide options to periodically trigger
events on other peripherals such as ADC, CMPs, Timers.
40.1
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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