NXP Semiconductors A3M34SL039 Page 33 Manual Download

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Date of release: September 2022

Document identifier: A3M34SL039

Summary of Contents for A3M34SL039

Page 1: ...unications to the module can be accomplished via either I2 C or SPI 3300 3700 MHz Typical LTE Performance Pout 8 W Avg VDD 29 Vdc 1 20 MHz LTE Input Signal PAR 8 dB 0 01 Probability on CCDF 1 Carrier Center Frequency Gain dB ACPR dBc PAE 3310 MHz 29 9 28 0 33 2 3500 MHz 29 6 31 6 37 1 3690 MHz 29 1 29 6 35 0 1 All data measured with device soldered in NXP reference circuit Features Advanced high p...

Page 2: ...overview 11 5 3 Tx enable control 12 5 4 Sense_DAC 12 5 5 VGS_DAC 13 5 6 Engineering Mode EM 13 6 Ordering information 13 7 Component layout and parts list 14 7 1 Component layout 14 7 2 Component designations and values 15 8 Temperature sensor 15 9 Communication interfaces 16 9 1 SPI 16 9 1 1 SPI timing diagram 16 9 1 2 SPI instruction set definition 16 9 2 I2 C 17 9 2 1 I2 C addressing 17 9 2 2 ...

Page 3: ...ration and function A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 3 33 1 Pinout configuration and function 1 1 Pin connections Figure 1 Pin connections ...

Page 4: ...JEDEC compatible 12 SDA SPI I2 C Serial Data Signal 1 8 V JEDEC compatible 13 CS_B Chip Selection Bar for SPI 1 8 V JEDEC compatible 15 Tx_EN PA Enable Signal 1 8 V JEDEC compatible 16 VCC_ 5V 5 V VCC Power Source for Autobias Chip 19 VDP1 Peaking Drain Supply Stage 1 20 VDP2 Peaking Drain Supply Stage 2 24 RFout RF Output Signal 50 Ohm 2 Electrical characteristics 2 1 Ratings 2 1 1 Maximum rating...

Page 5: ...1 2017 3A Charge Device Model per JS 002 2014 C3 2 1 4 Moisture sensitivity level Table 5 Moisture sensitivity level Test Methodology Rating Package Peak Temperature Unit Per JESD22 A113 IPC JEDEC J STD 020 3 260 C 2 2 Operating characteristics 2 2 1 Nominal DAC settings Table 6 Nominal DAC settings1 Characteristic Symbol Typ Unit Gate Quiescent DAC VDS 29 Vdc A_SENSE_DAC 36 A_VGS1_DAC 4 IDQ1C 31 ...

Page 6: ...ditive White Gaussian Noise AWGN with 10 dB PAR ISBW of 400 MHz at 30 Vdc 3 dB Input Overdrive from 8 W Avg Modulated Output Power No Device Degradation 2 2 4 Typical performance Table 9 Typical performance Characteristic Symbol Min Typ Max Unit Typical Performance3 In NXP Doherty Power Amplifier Module Reference Circuit 50 ohm system VDD 29 Vdc Nominal DAC Settings Tx_EN High Pout 8 W Avg 3500 MH...

Page 7: ...rwritten using the Engineering Mode EM sequence however the overwritten values do not persist after a power cycle or a reset The OTP memory can be programmed only by NXP during the manufacturing process and cannot be changed by the user The values in OTP memory have been selected to allow the device to operate in a wide variety of applications 3 2 Register map There are nine 8 bit user accessible ...

Page 8: ...Sense_DAC Reserved Group A Sense DAC OTP value 2 OTP COPY RW A_VGS1_DAC Group A VGS1 DAC OTP value 3 OTP COPY RW A_VGS2_DAC Group A VGS2 DAC OTP value 4 OTP COPY RW B_Sense_DAC Reserved Group B Sense DAC OTP value 5 OTP COPY RW B_VGS3_DAC Group B VGS3 DAC OTP value 6 OTP COPY RW B_VGS4_DAC Group B VGS4 DAC OTP value 7 14 Reserved 15 RO Temp_ADC Temperature Sensor 7 0 16 Reserved 17 Virtual W only ...

Page 9: ...itten after the reset operation is completed 0 No 4 Not available N A N A N A 0 3 Chip version bits Inserted by NXP to provide revision information Cannot be changed N A No R 1 A_Sense_DAC 6 7 Not available N A N A N A 0 5 Sense DAC A 6 bit logic value for carrier amplifiers DAC A sets the reference voltage to compare to the VDS across the reference device Minimum typical value is 6 b001000 and ma...

Page 10: ...final stage 8 h00 sets gate to equal ceiling voltage 8 hFF reduces gate voltage by a max value 8 h80 7 14 Reserved N A Not available N A N A N A No 15 Temp_ADC 0 7 Temperature sensor 8 bit DAC value 8 h00 is lowest temperature 8 hFF is highest temperature 8 h00 No R No 16 Reserved N A Not available N A N A N A No 17 EM_Passcode 0 7 Engineering Mode EM By writing 8 hE3 to this register the user can...

Page 11: ...is a duplicate of the carrier however the RF transistor peripheries and quiescent operating points will be different as required by the Doherty operation The module contains four RF LDMOS field effect transistors FET consisting of a driver and final for the carrier amplifier on a single IC die and a driver and final for the peaking amplifier on a single IC die Each IC die also contains a small per...

Page 12: ...n an ON state the RF FET gate terminals are internally decoupled with sufficient capacitance providing a low impedance for wide baseband signals The large capacitance also serves as a charge holding cap for reducing switching transient time in TDD operation In Tx OFF mode RF FET device gates are grounded shutting them OFF Table 12 TX_EN Off State Typical Currents Characteristic Typical Value Unit ...

Page 13: ...istors are manufactured on the same die in close proximity they exhibit similar process and temperature dependencies Both the peaking amplifier and the carrier amplifier operate in the same way with regard to the reference device and the RF transistors 5 6 Engineering Mode EM Flexibility exists to overwrite the OTP memory values if needed A special Engineering Mode EM is available to allow the use...

Page 14: ...022 Data Sheet Technical Data 14 33 7 Component layout and parts list 7 1 Component layout Figure 3 A3M34SL039 reference circuit component layout RFOUT RFIN Rev 4 0 C2 C4 C1 NC VDC2 A1 A0 GND GND TX_EN VCC_ 5V GND NC VDP1 VDP2 NC VCC VCC SDA CS_B SCLK GND GND B1 C14 aaa 042694 C15 L1 C17 C12 C10 R1 D157947 C18 Q1 ...

Page 15: ...D Murata Q1 Power Amplifier Module A3M34SL039 NXP R1 0 Ω 1 8 W Chip Resistor CRCW08050000Z0EA Vishay PCB Rogers RO4350B 0 020 εr 3 66 D139037 MTL Note Component numbers C3 C5 C6 C7 C8 C9 C11 C13 and C16 are intentionally omitted 8 Temperature sensor The temperature value is converted from the 8 bit temperature sense ADC value stored in the Temp_ADC register via the following equation Temperature C...

Page 16: ...omplies with SPI mode3 as shown in Figure 5 Figure 5 Serial interface timing diagram Table 16 Serial interface timing specification Symbol Parameter Min ns tSC Setup timing requirement of CS_B both rising and falling in relation to the rising edge of SCLK 50 tWH clk high duration 160 tWL clk low duration 160 tSD Date to clock rising edge setup 20 tHD clk rising edge to data hold time 20 tHC clk to...

Page 17: ...tocol standard It supports I2 C fast mode with a bit rate up to 400 Kbit s It also supports I2 C standard mode with bit rate up to 100 Kbit s 9 2 1 I2 C addressing The two external tri state address pins A0 and A1 use 5 V logic levels and are decoded into 7 bit I2 C addresses as shown in Table 16 The three LSBs of the 7 bit address are set via the A0 and A1 pins The four MSBs are the base address ...

Page 18: ...irfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 18 33 9 2 2 I2 C instruction set I2 C Write instruction Figure 7 I2 C Write instruction I2 C Read instruction Figure 8 I2 C Read instruction ...

Page 19: ...mark A STOP condition followed by a START condition resets the follower state machine and the Device ID read cannot be performed Also a STOP condition or a RESTART condition followed by an access to another follower device resets the follower state machine and the Device ID read cannot be performed 1 The leader sends the Reserved Device ID I2 C bus address followed by the R W bit set to 1 read 111...

Page 20: ...Follower Leader to Follower START 1111 1000 XXXXXXX 0 1 RESTART 1111 1001 3 bytes ID NACK STOP 9 3 I2 C electrical specification and timing for I O stages and bus lines Note VIL 0 3 VDD VIH 0 7 VDD Figure 10 I2 C electrical specification and timing for I O stages and bus lines aaa 042715 tf 70 30 SDA tf 70 30 S tr 70 30 70 30 tHD DAT SCLK 1 fSCLK 1st clock cycle 70 30 70 30 tr tVD DAT cont cont SD...

Page 21: ...ssion and the Acknowledge 3 A fast mode I2 C bus device can be used in a standard mode I2 C bus system but the requirement tSU DAT 250 ns must then be met This is automatically the case if the device does not stretch the LOW period of the SCLK signal If such a device does not stretch the LOW period of the SCLK signal it must output the next data bit to the SDA line tr max tSU DATA 1000 250 1250 ns...

Page 22: ...SP Pulse width of spikes that must be suppressed by the input filter 0 50 ns tof Output fall time from VIH min to VIL max Pullup res 250 ohm and max allowed load capacitance Cb 250 ns Cb Capacitive load for each bus line2 400 pF 1 VDD in this table refers to 1 8 V provided by the Leader 2 The maximum tf for the SDA and SCLK bus lines is specified at 300 ns This allows series protection resistors t...

Page 23: ...s to a 1 state at the same time Soft Reset bit will reset Engineering Mode EM The Soft Reset bit is easily accessible therefore be cautious of the accidental reset Tx_EN must not be active during an OTP refresh or during Engineering Mode 10 3 Group programming A common way of grouping A3M34SL039 modules is with parallel data inputs and unique chip CS_B connectivity In this case each module can be ...

Page 24: ...Design considerations A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 24 33 Figure 12 Parallel connectivity of grouping ...

Page 25: ...Product marking A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 25 33 11 Product marking Figure 13 Product marking ...

Page 26: ...Package information A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 26 33 12 Package information Figure 14 Package information ...

Page 27: ...Package information A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 27 33 Figure 14 Package information ...

Page 28: ...Package information A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 28 33 Figure 14 Package information ...

Page 29: ...Package information A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 29 33 Figure 14 Package information ...

Page 30: ...Package information A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 30 33 Figure 14 Package information ...

Page 31: ...Package information A3M34SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 31 33 Figure 14 Package information ...

Page 32: ...14 Failure analysis At this time because of the physical characteristics of the part failure analysis is limited to electrical signature analysis In cases where NXP is contractually obligated to perform failure analysis FA services full FA may be performed by third party vendors with moderate success For updates contact your local NXP Sales Office 15 Revision history The following table summarizes...

Page 33: ...ial or incidental damages Typical parameters that may be provided in NXP data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts NXP does not convey any license under its patent rights nor the rights of others NXP ...

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