Debug and Strapping
Jetson AGX Xavier Series Product
DG-09840-001_v2.5 | 117
15.2
JTAG and Debug UART
The following figure shows the JTAG and UART debug connections.
Figure 15-1. JTAG and UART Debug Connections
Jetson AGX Xavier
SoC
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_TRST_N
NVJTAG_SEL
NVDBG_SEL
10
0k
Ω
For Debug Use
DEBUG
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_TRST_N
NVJTAG_SEL
NVDBG_SEL
SYS_RESET_N
UART3_TX_DEBUG
UART3_RX_DEBUG
10
0k
Ω
See Note 1
Optional JTAG
connections
0
Ω
To PMIC
RTCK
TMS
TDI
TCK
TDO
TRST_N
RST
VDD_1V8_DBG
10
0k
Ω
UART3_TX
UART3_RX
AO
E58
B60
A60
D58
G61
H59
G60
H62
K60
L60
10
0k
Ω
0
Ω
0
Ω
Notes
:
1.
NVJTAG_SEL and JTAG_TRST_N must be low for normal operation and pulled to 1.8V for
Boundary Scan Mode. NVDBG is left unconnected (pulled down on module) for normal
operation and pulled to 1.8V for alternate debug modes (debug over USB, etc.). for Boundary
Scan test mode, JTAG_TRST_N must be driven high in the proper sequence. See the
Xavier
Boundary Scan Requirements and Usage document for details.
2.
Check preferred JTAG debugger documentation for JTAG PU/PD recommendations.
The Jetson AGX Xavier Developer Kit carrier board reference design implements a USB to
UART bridge. A simpler option is shown in the following figure. The UART3_DEBUG interface is
shown routed to a 6-pin header through level shifters.
Figure 15-2. Simple Debug UART Header Connections
Jetson AGX Xavier
SoC
1
2
3
4
5
6
Level Shifter
VCCB
VCCA
B1
A1
B2
A2
GND
DIR
Level Shifter
VCCA
VCCB
A1
B1
A2
B2
DIR
GND
10
0k
Ω
VDD_3V3
VDD_1V8
0.1uF
0.1uF
0.1uF
0.1uF
Serial Port
Header
UART3_TX_DEBUG
UART3_RX_DEBUG
UART3_TX
UART3_RX
AO
H62
K60
