NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
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sample
ADST
(ADCR[11])
ADF
(ADCR[0])
1
2
9
8
20
ADDRx[11:0]
ADC_CLK
ADDRx[11:0]
Figure 6.17-3 Single Mode Conversion Timing Diagram
6.17.5.3 Single-Cycle Scan Mode
In single-cycle scan mode, A/D conversion will sample and convert the specified channels once in
the sequence from the smallest number enabled channel to the largest number enabled channel.
1.
When the ADST bit (ADCR[11]) is set to 1 by software or external trigger input, A/D
conversion starts on the channel with the smallest number.
2.
When A/D conversion for each enabled channel is completed, the result is sequentially
transferred to the A/D data register corresponding to each channel.
3.
When the conversions of all the enabled channels are completed, the ADF bit (ADSR[0])
is set to 1. If the ADC interrupt function is enabled, the ADC interrupt occurs.
4.
After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D
converter enters idle state. If ADST is cleared to 0 before all enabled ADC channels
conversion done, ADC controller will finish current conversion and save the result to the
ADDRx of the current conversion channel.
An example timing diagram for single-cycle scan on enabled channels (0, 2, 3 and 8) is shown
below: