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Nuvoton NuMicro NUC029 Series Technical Reference Manual Download Page 304

NuMicro® NUC029LEE/NUC029SEE

 

32-bit Arm

®

 Cortex

®

-M0 Microcontroller 

Aug, 2018 

Page 

304

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497

 

Rev 1.00

 

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UC029

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Figure 6.11-2 Window Watchdog Timer Block Diagram 

6.11.4  Basic Configuration 

The  WWDT  peripheral  clock  is  enabled  in  APBCLK[0]  and  clock  source  can  be  selected  in 
CLKSEL2[17:16]. 

6.11.5  Functional Description 

The Window Watchdog Timer (WWDT) includes a 6-bit down counter with programmable 
prescale value to define different WWDT time-out intervals. 
The clock source of 6-bit WWDT is based on system clock divide 2048 (HCLK/2048) or internal 
10 kHz oscillator with a programmable 11-bit prescale counter value which controlled by 
PERIODSEL (WWDTCRL[11:8]) setting. Also, the correlate of PERIODSEL and prescale value 
are listed in the Table 6.11-1. 

PERIODSEL 

Prescaler Value 

Max. Time-Out Period 

Max. Time-Out Interval 

(WWDT_CLK=10 KHz) 

0000 

1 

1 * 64 * T

WWDT

 

6.4 ms 

0001 

2 

2 * 64 * T

WWDT

 

12.8 ms 

0010 

4 

4 * 64 * T

WWDT

 

25.6 ms 

0011 

8 

8 * 64 * T

WWDT

 

51.2 ms 

0100 

16 

16 * 64 * T

WWDT

 

102.4 ms 

0101 

32 

32 * 64 * T

WWDT

 

204.8 ms 

0110 

64 

64 * 64 * T

WWDT

 

409.6 ms 

0111 

128 

128 * 64 * T

WWDT

 

819.2 ms 

1000 

192 

192 * 64 * T

WWDT

 

1.2288 s 

1001 

256 

256 * 64 * T

WWDT

 

1.6384 s 

1010 

384 

384 * 64 * T

WWDT

 

2.4576 s 

1011 

512 

512 * 64 * T

WWDT

 

3.2768 s 

1100 

768 

768 * 64 * T

WWDT

 

4.9152 s 

1101 

1024 

1024 * 64 * T

WWDT

 

6.5536 s 

1110 

1536 

1536 * 64 * T

WWDT

 

9.8304 s 

1111 

2048 

2048 * 64 * T

WWDT

 

13.1072 s 

Table 6.11-1 Window Watchdog Timer Prescale Value Selection 

 

  WWDT Counting 

When the WWDTEN bit is set, WWDT down counter will start counting from 0x3F to 0. To prevent 
program  runs  to  disable  WWDT  counter  counting  unexpected,  the  WWDT  control  register 
WWDTCR can only be written once after chip is powered on or reset. User cannot disable WWDT 
counter counting (WWDTEN), change counter prescale period (PERIODSEL) or change  window 
compare  value  (WINCMP)  while  WWDTEN  (WWDTCR[0])  bit  has  been  enabled  by  software 

Summary of Contents for NuMicro NUC029 Series

Page 1: ...the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuM...

Page 2: ...4 4 Pin Description 22 4 4 1 NuMicro NUC029LEE NUC029SEE Pin Description 22 5 BLOCK DIAGRAM 27 5 1 NuMicro NUC029LEE NUC029SEE Block Diagram 27 6 FUNCTIONAL DESCRIPTION 28 6 1 ARM Cortex M0 Core 28 6...

Page 3: ...Overview 164 6 5 2 Features 164 6 5 3 Block Diagram 165 6 5 4 Functional Description 165 6 5 5 Register Map 171 6 5 6 Register Description 172 6 6 General Purpose I O GPIO 176 6 6 1 Overview 176 6 6 2...

Page 4: ...ap 265 6 9 7 Register Description 267 6 10Watchdog Timer WDT 295 6 10 1 Overview 295 6 10 2 Features 295 6 10 3 Block Diagram 296 6 10 4 Basic Configuration 297 6 10 5 Functional Description 297 6 10...

Page 5: ...2 Features 389 6 14 3 Basic Configuration 390 6 14 4 Block Diagram 390 6 14 5 Functional Description 390 6 14 6 Example for Random Read on EEPROM 403 6 14 7 Register Map 405 6 14 8 Register Descripti...

Page 6: ...g to Digital Converter ADC 472 6 17 1 Overview 472 6 17 2 Features 472 6 17 3 Block Diagram 473 6 17 4 Basic Configuration 473 6 17 5 Functional Description 474 6 17 6 Register Map 481 6 17 7 Register...

Page 7: ...ange for Booting from APROM and LDROM 149 Figure 6 4 4 Executable Range of Code with IAP Function Enabled 150 Figure 6 4 5 Example Flow of Boot Selection by BS Bit 151 Figure 6 4 6 ISP Flow Example 15...

Page 8: ...nterrupt Architecture Diagram 262 Figure 6 10 1 Watchdog Timer Clock Control 296 Figure 6 10 2 Watchdog Timer Block Diagram 296 Figure 6 10 3 Watchdog Timer Time out Interval and Reset Period Timing 2...

Page 9: ...Mode Control Flow 395 Figure 6 14 11 Master Receiver Mode Control Flow 396 Figure 6 14 12 Save Mode Control Flow 397 Figure 6 14 13 GC Mode 398 Figure 6 14 14 Arbitration Lost 399 Figure 6 14 15 I 2...

Page 10: ...ontroller Block Diagram 473 Figure 6 17 2 ADC Clock Control 474 Figure 6 17 3 Single Mode Conversion Timing Diagram 475 Figure 6 17 4 Single Cycle Scan on Enabled Channels Timing Diagram 476 Figure 6...

Page 11: ...out Interval Period Selection 298 Table 6 11 1 Window Watchdog Timer Prescale Value Selection 304 Table 6 11 2 WINCMP Setting Limitation 306 Table 6 13 1 UART Interface Controller Pin 339 Table 6 13 2...

Page 12: ...029 series is embedded with the ARM Cortex M0 core running up to 72 MHz and features 128 Kbytes flash 16K bytes SRAM and 8 Kbytes loader ROM for the ISP It is also equipped with plenty of peripheral d...

Page 13: ...tion for different applications Built in 22 1184 MHz high speed oscillator for system operation Trimmed to 1 at 25 and VDD 5 V Trimmed to 3 at 40 105 and VDD 2 5 V 5 5 V Built in 48 MHz internal high...

Page 14: ...t or Auto reload mode Up to six 16 bit digital capture timers shared with PWM timers providing six rising falling capture inputs Supports Capture interrupt UART Up to three UART controllers UART ports...

Page 15: ...ogrammable endpoints Includes 512 Bytes internal SRAM as USB buffer Provides remote wake up capability Supports Crystal less function ADC 12 bit SAR ADC with 1 MSPS chip working at 5V Up to 12 ch sing...

Page 16: ...FIFO First In First Out FMC Flash Memory Controller FPU Floating point Unit GPIO General Purpose Input Output HCLK The Clock of Advanced High Performance Bus HIRC 22 1184 MHz Internal High Speed RC O...

Page 17: ...SEE TECHNICAL REFERENCE MANUAL SPI Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver Transmitter UCID Un...

Page 18: ...MANUAL 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4 1 NuMicro NUC029 Series Selection Code CPU core ARM Cortex M0 Package Type F TSSOP 20 T QFN33 5x5 Z QFN33 4x4 N QFN48 7x7 L LQFP 48 7x7 S LQFP...

Page 19: ...NUC029ZAN 64 4 4 4 24 4 2 1 2 5 5 3 2 QFN33 5 5 40 to 85 NUC029LAN 64 4 4 4 40 4 2 2 2 8 8 4 LQFP48 40 to 85 NUC029LDE 68 8 Conf 4 42 4 4 1 2 3 12 8 LQFP48 40 to 105 NUC029SDE 68 8 Conf 4 56 4 4 1 2 3...

Page 20: ...PF 0 XT1_IN PF 1 nRESET CLKO TM0 STADC PB 8 PA 4 ADC4 AD9 PA 3 ADC3 AD10 PA 2 ADC2 AD11 PA 1 ADC1 AD12 PA 0 ADC0 AV SS ICE_CLK ICE_DAT PA 12 PWM0 AD13 PA 13 PWM1 AD14 PA 14 PWM2 AD15 PA 15 PWM3 PC 8 S...

Page 21: ...0_EXT INT1 PB 15 XT1_OUT PF 0 XT1_IN PF 1 nRESET CLKO TM0 STADC PB 8 PA 4 ADC4 PA 3 ADC3 PA 2 ADC2 PA 1 ADC1 PA 0 ADC0 AV SS ICE_CLK ICE_DAT PA 12 PWM0 PA 13 PWM1 PA 14 PWM2 PA 15 PWM3 AVDD PVSS PC 0...

Page 22: ...ed crystal input pin 6 4 PA 11 I O General purpose digital I O pin I2C1_SCL I O I2 C1 clock pin nRD O EBI read enable output pin 7 5 PA 10 I O General purpose digital I O pin I2C1_SDA I O I2 C1 data i...

Page 23: ...t pin for UART0 22 18 PB 1 I O General purpose digital I O pin UART0_TXD O Data transmitter output pin for UART0 23 19 PB 2 I O General purpose digital I O pin UART0_nRTS O Request to Send output pin...

Page 24: ...digital I O pin TM1 I O Timer1 event counter input toggle output UART2_TXD O Data transmitter output pin for UART2 33 PC 11 I O General purpose digital I O pin SPI1_MOSI0 I O 1st SPI1 MOSI Master Out...

Page 25: ...bit12 46 34 PA 2 I O General purpose digital I O pin ADC2 AI ADC2 analog input AD11 I O EBI Address Data bus bit11 47 35 PA 3 I O General purpose digital I O pin ADC3 AI ADC3 analog input AD10 I O EBI...

Page 26: ...nt counter input toggle output ADC11 AI ADC11 analog input AD6 I O EBI Address Data bus bit6 58 44 PF 0 I O General purpose digital I O pin XT1_OUT O External 4 24 MHz high speed crystal output pin 59...

Page 27: ...ace 32 bit Timer x 4 RTC PWM Capture Timer x 6 Watchdog Timer 12 bit ADC x 12 Power Control Clock Control LDO Power On Reset LVR Brownout Detection High Speed Oscillator 48 MHz High Speed Crystal Osc...

Page 28: ...ctored Interrupt Controller NVIC Breakpoint and Watchpoint Unit Debugger Interface Bus Matrix Debug Access Port DAP Debug Cortex M0 processor Cortex M0 Components Wakeup Interrupt Controller WIC Inter...

Page 29: ...input Supports for both level sensitive and pulse sensitive interrupt lines Supports Wake up Interrupt Controller WIC and providing Ultra low Power Sleep mode Debug support Four hardware breakpoints T...

Page 30: ...ored Interrupt Controller NVIC System Control registers 6 2 2 System Reset The system reset can be issued by one of the following listed events For these reset event flags can be read by RSTSRC regist...

Page 31: ...e RTC and external 32 768 kHz crystal The outputs of internal voltage regulators LDO and VDD33 require an external capacitor which should be located close to the corresponding pin Analog power AVDD sh...

Page 32: ...heral DMA Control Registers 0x5000_C000 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_0000 0x5001_03FF EBI_BA External Bus Interface Control Registers APB1 Controllers Space 0x4000_0000 0x4...

Page 33: ...r can check the protection disable bit at address 0x5000_0100 bit0 1 is protection disable and 0 is protection enable Then user can update the target protected register value and then write any data t...

Page 34: ...te Protect ISPCON 3 APUEN APROM Update Enable Bit Write Protect ISPCON 1 BS Boot Select Write Protect ISPCON 0 ISPEN ISP Enable Bit Write Protect ISPTRG 0 ISPGO ISP Start Trigger Write Protection Bit...

Page 35: ...on to 01 and the auto trim function will be enabled Interrupt status bit FREQ_LOCK SYS_IRCTSTS 0 HIRC frequency lock status 1 indicates the HIRC output frequency is accurate within 0 25 deviation To g...

Page 36: ...000_0000 GPB_MFP GCR_BA 0x34 R W GPIOB Multiple Function and Input Type Control Register 0x0000_0000 GPC_MFP GCR_BA 0x38 R W GPIOC Multiple Function and Input Type Control Register 0x0000_0000 GPE_MFP...

Page 37: ...W Description Reset Value PDID GCR_BA 0x00 R Part Device Identification Number Register 0x2014_0018 1 1 Each part number has a unique default reset value 31 30 29 28 27 26 25 24 PDID 23 22 21 20 19 18...

Page 38: ...ry controller FMC 0 No reset from CPU 1 Cortex M0 CPU kernel and FMC are reset by software setting CPU_RST IPRSTC1 1 to 1 Note Write 1 to clear this bit to 0 6 Reserved Reserved 5 RSTS_SYS SYS Reset F...

Page 39: ...clear this bit to 0 Note2 Watchdog Timer register WTRF WTCR 2 bit is set if the system has been reset by WDT time out reset Window Watchdog Timer register WWDTRF WWDTSR bit is set if the system has b...

Page 40: ...PDMA Controller Reset Write Protect Setting this bit to 1 will generate a reset signal to the PDMA User needs to set this bit to 0 to release from reset state 0 PDMA controller normal operation 1 PDMA...

Page 41: ...he same as the POR reset all the chip controllers are reset and the chip setting from flash are also reload For the difference between CHIP_RST and SYSRESETREQ please refer to section 5 2 2 0 CHIP nor...

Page 42: ...2 11 10 9 8 Reserved SPI1_RST SPI0_RST Reserved I2C1_RST I2C0_RST 7 6 5 4 3 2 1 0 Reserved TMR3_RST TMR2_RST TMR1_RST TMR0_RST GPIO_RST Reserved Bits Description 31 39 Reserved Reserved 28 ADC_RST ADC...

Page 43: ...0 I2 C1 controller normal operation 1 I2 C1 controller reset 8 I2C0_RST I2 C0 Controller Reset 0 I2 C0 controller normal operation 1 I2 C0 controller reset 7 6 Reserved Reserved 5 TMR3_RST Timer3 Con...

Page 44: ...Voltage Reset function Enabled After enabling the bit the LVR function will be active with 100us delay for LVR output stable default Note This bit is the protected bit and programming it needs to wri...

Page 45: ...IC BOD interrupt or disabling BOD function set BOD_EN low Note2 The default value is set by flash controller user configuration register CBORST CONFIG0 20 bit Note3 This bit is the protected bit It me...

Page 46: ...14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VTEMP_EN Bits Description 31 1 Reserved Reserved 0 VTEMP_EN Temperature Sensor Enable Bit This bit is used to enable disable temperature sensor fun...

Page 47: ...rotect When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again User can disable internal POR circuit to avoid un...

Page 48: ...unction is selected 14 GPA_MFP14 PA 14 Pin Function Selection Bits EBI_HB_EN 7 ALT_MFP 23 EBI_EN ALT_MFP 11 and GPA_MFP 14 determine the PA 14 function EBI_HB_EN EBI_EN GPA_MFP14 value and function ma...

Page 49: ...PA_MFP8 PA 8 Pin Function Selection Bit GPA_MFP 8 determines the PA 9 function 0 GPIO function is selected to the pin PA 8 1 I2C0_SDA function is selected to the pin PA 8 7 GPA_MFP7 Reserved 6 GPA_MFP...

Page 50: ...Function Selection Bits EBI_HB_EN 3 ALT_MFP 19 EBI_EN ALT_MFP 11 and GPA_MFP 2 determine the PA 2 function EBI_HB_EN EBI_EN GPA_MFP2 value and function mapping is as following list 0 0 0 GPIO functio...

Page 51: ...LT_MFP2 1 PB15_T0EX ALT_MFP 24 PB15_TM0 ALT_MFP2 2 and GPB_MFP 15 determine the PB 15 function PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15 value and function mapping is as following list 0 0 0 0 GPIO fun...

Page 52: ...ion is selected 0 1 TM0 function is selected to the pin PB 8 1 0 STADC function is selected to the pin PB 8 1 1 CLKO function is selected to the pin PB 8 7 GPB_MFP7 PB 7 Pin Function Selection Bit EBI...

Page 53: ...RL_EN ALT_MFP 13 EBI_EN ALT_MFP 11 PB2_TM2 ALT_MFP2 4 PB2_T2EX ALT_MFP 26 and GPB_MFP 2 determine the PB 2 function EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2 value and function mapping is as follow...

Page 54: ...its EBI_EN ALT_MFP 11 and GPC_MFP 15 determine the PC 15 function EBI_EN GPC_MFP15 value and function mapping is as following list 0 0 GPIO function is selected 0 1 ADC9 function is selected 1 1 AD3 f...

Page 55: ...ts EBI_EN ALT_MFP 11 and GPC_MFP 7 determine the PC 7 function EBI_EN GPC_MFP7 value and function mapping is as following list 0 0 0 GPIO function is selected 0 0 1 ADC7 function is selected 1 0 1 AD5...

Page 56: ...E 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved GPE_MFP5 Reserved Bits Description 31 16 GPE_TYPEn Trigger Function Selection 0 GPIOE 15 0 I O input Schmitt Trigger function Disabled 1 GPIOE...

Page 57: ...1 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved GPF_MFP1 GPF_MFP0 Bits Description 31 20 Reserved Reserved 19 16 GPF_TYPEn Trigger Function Selection 0 GPIOF 3 0 I O input Schmitt Trigger function Disabled...

Page 58: ...eserved 29 PB8_CLKO PB 8 Pin Alternative Function Selection Bits PB8_CLKO ALT_MFP 29 and GPB_MFP 8 determine the PB 8 function PB8_CLKO GPB_MFP8 value and function mapping is as following list 0 0 GPI...

Page 59: ..._EBI ALT_MFP2 1 PB15_T0EX ALT_MFP 24 PB15_TM0 ALT_MFP2 2 and GPB_MFP 15 determine the PB 15 function PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15 value and function mapping is as following list 0 0 0 0 GP...

Page 60: ...GPIO function is selected 0 0 1 ADC3 function is selected 1 1 1 AD10 function is selected 17 EBI_HB_EN 1 Bits EBI_HB_EN 1 ALT_MFP 17 EBI_EN ALT_MFP 11 and GPA_MFP 4 determine the PA 4 function EBI_HB_...

Page 61: ...7 0 and EBI_MCLK_EN for some GPIO to switch to EBI function AD 15 8 MCLK 10 5 Reserved Reserved 4 PB11_PWM4 PB 11 Pin Alternative Function Selection Bits PB11_PWM4 ALT_MFP 4 and GPB_MFP 11 determine t...

Page 62: ...BI_EN ALT_MFP 11 PB3_TM3 ALT_MFP2 5 PB3_T3EX ALT_MFP 27 and GPB_MFP 3 determine the PB 3 function EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3 value and function mapping is as following list 0 0 0 0 0...

Page 63: ...ng list 0 0 0 0 GPIO function is selected 0 0 0 1 INT1 function is selected 0 0 1 1 TM0 function is selected 0 1 0 0 ADC11 function is selected 0 1 0 1 TM0_EXT function is selected 1 0 0 1 AD6 functio...

Page 64: ...ter will be reset If the trim value update counter reached this limitation value and frequency of HIRC still doesn t lock the auto trim operation will be disabled and TRIM_SEL will be cleared to 00 00...

Page 65: ...is 00 the HIRC auto trim function is disabled During auto trim operation if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached this field will be clear...

Page 66: ...o1 and CLKERR_INT IRCTRIMINT 2 is set during auto trim operation An interrupt will be triggered to notify the clock frequency is inaccuracy 0 CLKERR_INT IRCTRIMINT 2 status to trigger an interrupt to...

Page 67: ...is set to 1 If this bit is set and CLKERR_IEN IRCTIEN 2 is high an interrupt will be triggered to notify the clock frequency is inaccuracy Write 1 to clear this to 0 0 Clock frequency is accurate 1 C...

Page 68: ...The trim operation is keep going if clock is inaccuracy 1 The trim operation is stopped if clock is inaccuracy 7 6 RETRYCNT Trim Value Update Limitation Count This field defines that how many times th...

Page 69: ...t as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock 3 2 Reserved Reserved 1 0 FREQSEL Trim Frequency Selection This field indic...

Page 70: ...set to1 and CLKERRIF SYS_HIRCTSTS 2 is set during auto trim operation an interrupt will be triggered to notify the clock frequency is inaccuracy 0 Disable CLKERRIF SYS_HIRCTSTS 2 status to trigger an...

Page 71: ...n indicate that clock frequency is inaccuracy Once this bit is set to 1 the auto trim operation stopped and FREQSEL SYS_HIRCTCTL 1 0 will be cleared to 00 by hardware automatically if CESTOPEN SYS_HIR...

Page 72: ...ates the HIRC frequency is locked This is a status bit and doesn t trigger any interrupt Write 1 to clear this to 0 This bit will be set automatically if the frequecy is lock and the RC_TRIM is enable...

Page 73: ...mpleted the REGPROTDIS bit will be set to 1 and write protection registers can be normal write 0 REGPROTDIS Register Write Protection Disable Index Read Only 0 Write protection is enabled for writing...

Page 74: ...p to the value in the SysTick Reload Value Register SYST_RVR on the next clock cycle then decrement on subsequent clocks When the counter transitions to 0 the COUNTFLAG status bit is set The COUNTFLAG...

Page 75: ...m Timer Control Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value SYST Base Address SCS_BA 0xE000_E000 SYST_CSR SCS_BA 0x10 R W SysTick Control...

Page 76: ...set by a count transition from 1 to 0 COUNTFLAG is cleared on read or by a write to the Current Value register 15 3 Reserved Reserved 2 CLKSRC System Tick Clock Source Selection If CLKSRC SYST_CSR 2...

Page 77: ...e Register SYST_RVR Register Offset R W Description Reset Value SYST_RVR SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 15 14...

Page 78: ...Tick Current Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURRENT 15 14 13 12 11 10 9 8 CURRENT 7 6 5 4 3 2 1 0 CURRENT Bits Description 31 24 Reserved Reserved...

Page 79: ...r When an interrupt is accepted the starting address of the interrupt service routine ISR is fetched from a vector table in memory There is no need to determine which interrupt is accepted and branch...

Page 80: ...l 11 Configurable Reserved 12 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt IRQ0 IRQ31 16 47 Configurable Table 6 2 2 Exception Model Vector Number Interrupt Number Bit In Inter...

Page 81: ...RTC_INT RTC Real Time Clock interrupt Table 6 2 3 System Interrupt Map 6 2 10 2Vector Table When an interrupt is accepted the processor will automatically fetch the starting address of the interrupt s...

Page 82: ...on return Clearing the enable bit prevents new activations of the associated interrupt NVIC interrupts can be pended un pended using a complementary pair of registers to those used to enable disable t...

Page 83: ...g Control Register 0x0000_0000 NVIC_ICPR SCS_BA 0x280 R W IRQ0 IRQ31 Clear pending Control Register 0x0000_0000 NVIC_IPR0 SCS_BA 0x400 R W IRQ0 IRQ3 Priority Control Register 0x0000_0000 NVIC_IPR1 SCS...

Page 84: ...enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 SETENA 23 22 21 20 19 18 17 16 SETENA 15 14 13 12 11 10 9 8 SETENA 7 6 5 4 3 2 1 0 SETENA Bits Description 31 0 SETENA Interrupt Enable Regi...

Page 85: ...ister 0x0000_0000 31 30 29 28 27 26 25 24 CLRENA 23 22 21 20 19 18 17 16 CLRENA 15 14 13 12 11 10 9 8 CLRENA 7 6 5 4 3 2 1 0 CLRENA Bits Description 31 0 CLRENA Interrupt Disable Bits Disable one or m...

Page 86: ...trol Register 0x0000_0000 31 30 29 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEND 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND Bits Description 31 0 SETPEND Set Interrupt Pending Regi...

Page 87: ...trol Register 0x0000_0000 31 30 29 28 27 26 25 24 CLRPEND 23 22 21 20 19 18 17 16 CLRPEND 15 14 13 12 11 10 9 8 CLRPEND 7 6 5 4 3 2 1 0 CLRPEND Bits Description 31 0 CLRPEND Clear Interrupt Pending Re...

Page 88: ...16 PRI_2 Reserved 15 14 13 12 11 10 9 8 PRI_1 Reserved 7 6 5 4 3 2 1 0 PRI_0 Reserved Bits Description 31 30 PRI_3 Priority Of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority 29...

Page 89: ...16 PRI_6 Reserved 15 14 13 12 11 10 9 8 PRI_5 Reserved 7 6 5 4 3 2 1 0 PRI_4 Reserved Bits Description 31 30 PRI_7 Priority Of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority 29...

Page 90: ...6 PRI_10 Reserved 15 14 13 12 11 10 9 8 PRI_9 Reserved 7 6 5 4 3 2 1 0 PRI_8 Reserved Bits Description 31 30 PRI_11 Priority Of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority 2...

Page 91: ...PRI_14 Reserved 15 14 13 12 11 10 9 8 PRI_13 Reserved 7 6 5 4 3 2 1 0 PRI_12 Reserved Bits Description 31 30 PRI_15 Priority Of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority 2...

Page 92: ...PRI_18 Reserved 15 14 13 12 11 10 9 8 PRI_17 Reserved 7 6 5 4 3 2 1 0 PRI_16 Reserved Bits Description 31 30 PRI_19 Priority Of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority 2...

Page 93: ...PRI_22 Reserved 15 14 13 12 11 10 9 8 PRI_21 Reserved 7 6 5 4 3 2 1 0 PRI_20 Reserved Bits Description 31 30 PRI_23 Priority Of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority 2...

Page 94: ...PRI_26 Reserved 15 14 13 12 11 10 9 8 PRI_25 Reserved 7 6 5 4 3 2 1 0 PRI_24 Reserved Bits Description 31 30 PRI_27 Priority Of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority 2...

Page 95: ...PRI_30 Reserved 15 14 13 12 11 10 9 8 PRI_29 Reserved 7 6 5 4 3 2 1 0 PRI_28 Reserved Bits Description 31 30 PRI_31 Priority Of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority 2...

Page 96: ...RQ5_SRC INT_BA 0x14 R IRQ5 GPC E F Interrupt Source Identity 0xXXXX_XXXX IRQ6_SRC INT_BA 0x18 R IRQ6 PWMA Interrupt Source Identity 0xXXXX_XXXX IRQ7_SRC INT_BA 0x1C R IRQ7 PWMB Interrupt Source Identi...

Page 97: ...xXXXX_XXXX IRQ27_SRC INT_BA 0x6C R Reserved 0xXXXX_XXXX IRQ28_SRC INT_BA 0x70 R IRQ28 PWRWU Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA 0x74 R IRQ29 ADC Interrupt Source Identity 0xXXXX_XXX...

Page 98: ...24 R IRQ9 TMR1 Interrupt Source Identity 0xXXXX_XXXX IRQ10_SRC INT_BA 0x28 R IRQ10 TMR2 Interrupt Source Identity 0xXXXX_XXXX IRQ11_SRC INT_BA 0x2C R IRQ11 TMR3 Interrupt Source Identity 0xXXXX_XXXX I...

Page 99: ...XXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved INT_SRC Bits Description 31 4 Reserved Reserved 3 0 INT_SRC Interrup...

Page 100: ...BA 0x20 8 Bit2 0 Bit1 0 Bit0 TMR0_INT 2 0 INT_BA 0x24 9 Bit2 0 Bit1 0 Bit0 TMR1_INT 2 0 INT_BA 0x28 10 Bit2 0 Bit1 0 Bit0 TMR2_INT 2 0 INT_BA 0x2C 11 Bit2 0 Bit1 0 Bit0 TMR3_INT 2 0 INT_BA 0x30 12 Bit...

Page 101: ...1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 2 0 INT_BA 0x68 26 Bit2 0 Bit1 0 Bit0 PDMA_INT 2 0 INT_BA 0x70 28 Bit2 0 Bit1 0 Bit0 PWRWU_INT 2 0 INT_BA 0x74 29 Bit2 0 Bit1 0 Bit0 ADC_IN...

Page 102: ...7 16 Reserved 15 14 13 12 11 10 9 8 Reserved NMI_EN 7 6 5 4 3 2 1 0 Reserved NMI_SEL Bits Description 31 8 Reserved Reserved 8 NMI_EN NMI Interrupt Enable Bit Write Protect 0 NMI interrupt Disabled 1...

Page 103: ...6 5 4 3 2 1 0 MCU_IRQ Bits Description 31 0 MCU_IRQ MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex M0 There are...

Page 104: ...pt Request Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FAST_IRQ Bits Description 31 1 Reserve...

Page 105: ...RM Cortex M0 Technical Reference Manual and ARM v6 M Architecture Reference Manual 6 2 11 1System Control Register Map R read only W write only R W both read and write Register Offset R W Description...

Page 106: ...BA 0xD00 R CPUID Register 0x410C_C200 31 30 29 28 27 26 25 24 IMPLEMENTER 23 22 21 20 19 18 17 16 Reserved PART 15 14 13 12 11 10 9 8 PARTNO 7 6 5 4 3 2 1 0 PARTNO REVISION Bits Description 31 24 IMPL...

Page 107: ...e NMI is the highest priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit Entering the handler then clears this bit to 0 This means...

Page 108: ...must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time 24 Reserved Reserved 23 ISRPREEMPT If Set A Pending Exception Will Be Serviced On Exit From The Debug Halt State This bit is read on...

Page 109: ...Access Key Write Operation When writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored The VECTORKEY filed is used to prevent accidental...

Page 110: ...g disabled interrupts can wake up the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event...

Page 111: ...egister Offset R W Description Reset Value SHPR2 SCS_BA 0xD1C R W System Handler Priority Register 2 0x0000_0000 31 30 29 28 27 26 25 24 PRI_11 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 112: ...andler Priority Register 3 0x0000_0000 31 30 29 28 27 26 25 24 PRI_15 Reserved 23 22 21 20 19 18 17 16 PRI_14 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PR...

Page 113: ...wake up interrupt source triggered to leave Power down mode In the Power down mode the clock controller turns off the 4 24 MHz external high speed crystal oscillator and 22 1184 48 MHz internal high s...

Page 114: ...LCON 19 PLL FOUT 10 kHz LIRC OSC10K_EN PWRCON 3 HXT HIRC LIRC Legend LXT 32 768 kHz external low speed crystal oscillator HXT 4 24 MHz external high speed crystal oscillator HIRC 22 1184 MHz internal...

Page 115: ...0 SYST_CSR 2 CPUCLK 1 HCLK_N 1 PCLK CPUCLK HCLK 11 01 00 PLLFOUT 4 24 MHz HCLK CLKSEL1 3 2 External trigger CLKSEL1 22 20 CLKSEL1 18 16 CLKSEL1 14 12 CLKSEL1 10 8 011 010 001 000 HCLK 4 24 MHz 22 118...

Page 116: ...AHB APB CPUCLK HCLK PCLK Note Before clock switching both the pre selected and newly selected clock sources must be turned on and stable Figure 6 3 3 System Clock Block Diagram The clock source of Sys...

Page 117: ...ft register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin Therefore there are 16 options of power of 2 divided clocks with the frequency from Fin 2 1 to Fin 2 16 w...

Page 118: ...ENCE MANUAL 0000 0001 1110 1111 16 to 1 MUX 1 2 1 22 1 23 1 215 1 216 FSEL FRQDIV 3 0 FRQDIV_CLK 16 chained divide by 2 counter DIVIDER_EN FRQDIV 4 Enable divide by 2 counter 0 1 DIVIDER1 FRQDIV 5 CLK...

Page 119: ...s Clock Enable Control Register 0x0000_0005 APBCLK CLK_BA 0x08 R W APB Devices Clock Enable Control Register 0x0000_000X CLKSTATUS CLK_BA 0x0C R W Clock Status Monitor Register 0x0000_00XX CLKSEL0 CLK...

Page 120: ...gh speed RC oscillator HIRC48 Disabled 1 48 MHz internal high speed RC oscillator HIRC48 Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 11 9 Reserved Reserved 8 PD_WAIT_CPU...

Page 121: ...when both PD_WU_STS and PD_WU_INT_EN are high Note2 This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable register protection Refer to the...

Page 122: ...100 0 XTL12M_EN 4 24 MHz External High Speed Crystal Oscillator HXT Enable Bit Write Protect The bit default value is set by flash controller user configuration register CONFIG0 26 24 When the default...

Page 123: ...x 0 YES Only CPU clock disabled Power down mode CPU entering Deep Sleep mode 1 1 1 YES Most clocks are disabled except 10 kHz and 32 768 kHz only RTC WDT Timer PWM peripheral clock still enable if th...

Page 124: ...able Control Register 0x0000_0005 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved EBI_EN ISP_EN PDMA_EN Reserved Bits Descript...

Page 125: ...erved SPI1_EN SPI0_EN Reserved I2C1_EN I2C0_EN 7 6 5 4 3 2 1 0 Reserved FDIV_EN TMR3_EN TMR2_EN TMR1_EN TMR0_EN RTC_EN WDT_EN Bits Description 31 29 Reserved Reserved 28 ADC_EN Analog Digital Converte...

Page 126: ...ivider Output Clock Enable Bit 0 FDIV clock Disabled 1 FDIV clock Enabled 5 TMR3_EN Timer3 Clock Enable Bit 0 Timer3 clock Disabled 1 Timer3 clock Enabled 4 TMR2_EN Timer2 Clock Enable Bit 0 Timer2 cl...

Page 127: ...Page 127 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL Note This bit is the protected bit and programming it needs to write 59h 16h and 88h to address 0x5000_0100 to disable r...

Page 128: ...e will keep old clock until the new clock is stable During the period that waiting new clock stable this bit will be an index shows system clock source is not match as user wanted 6 Reserved Reserved...

Page 129: ...Read Only 0 32 768 kHz external low speed crystal oscillator LXT clock is not stable or disabled 1 32 768 kHz external low speed crystal oscillator LXT clock is stable and enabled 0 XTL12M_STB 4 24 M...

Page 130: ...ternal low speed crystal oscillator clock 010 Clock source from 4 24 MHz external high speed crystal oscillator clock 2 011 Clock source from HCLK 2 111 Clock source from 22 1184 MHz internal high spe...

Page 131: ...speed crystal oscillator clock 010 Clock source from PLL clock 011 Clock source from 10 kHz internal low speed RC oscillator clock 111 Clock source from 22 1184 MHz internalhigh speed RC oscillator c...

Page 132: ...M2 and PWM3 defined by PWM23_S list below 00 Clock source from 4 24 MHz external high speed crystal oscillator clock 01 Clock source from 32 768 kHz external low speed crystal oscillator clock 10 Cloc...

Page 133: ...IMER2 Clock Source Selection 000 Clock source from external 4 24 MHz high speed crystal oscillator clock 001 Clock source from external 32 768 kHz low speed crystal oscillator clock 010 Clock source f...

Page 134: ...ck Source Select 00 Clock source from 4 24 MHz external high speed crystal oscillator clock 01 Clock source from PLL clock 10 Clock source from HCLK 11 Clock source from 22 1184 MHz internal high spee...

Page 135: ...clock 17 16 WWDT_S Window Watchdog Timer Clock Source Selection 10 Clock source from HCLK 2048 clock 11 Clock source from 10 kHz internal low speed RC oscillator clock 15 11 Reserved Reserved 10 PWM4...

Page 136: ...fined by PWM01_S list below 00 Clock source from 4 24 MHz external high speed crystal oscillator clock 01 Clock source from 32 768 kHz external low speed crystal oscillator clock 10 Clock source from...

Page 137: ...age 137 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 01 Clock source from 32 768 kHz external low speed crystal oscillator clock 10 Clock source from HCLK 11 Clock source fro...

Page 138: ...3 12 11 10 9 8 Reserved UART_N 7 6 5 4 3 2 1 0 USB_N HCLK_N Bits Description 15 12 Reserved Reserved 23 16 ADC_N ADC Clock Divide Number From ADC Clock Source ADC clock frequency ADC clock source freq...

Page 139: ...6 5 4 3 2 1 0 FB_DV Bits Description 31 20 Reserved Reserved 19 PLL_SRC PLL Source Clock Selection 0 PLL source clock from 4 24 MHz external high speed crystal oscillator 1 PLL source clock from 22 1...

Page 140: ...MHz FIN MHz 150 2 3 2 MHz NR FIN KHz 5 7 2 800 3 preferred is 120 200 100 FCO MHz MHz NR NF FIN FCO MHz Symbol Description FOUT Output Clock Frequency FIN Input Reference Clock Frequency NR Input Divi...

Page 141: ...Enable Bit 0 1 Hz clock output for 32 768 kHz external low speed crystal oscillator clock frequency compensation Disabled 1 1 Hz clock output for 32 768 kHz external low speed crystal oscillator cloc...

Page 142: ...FIG0 By the way the NuMicro NUC029LEE NUC029SEE also provides additional Data Flash for user to store some application dependent data The Data Flash is shared with original 128 KB program memory and i...

Page 143: ...ro interface timing control logic The block diagram of flash memory controller is shown as follows AHB Slave Interface ISP Controller Application Program Memory CBS 11b 0x0000_0000 0x0001_FFFF Flash O...

Page 144: ...e 128 KB Data Flash size User configuration provides several bytes to control system logic such as flash security lock boot select Brown out voltage level Data Flash base address etc User configuratio...

Page 145: ...REFERENCE MANUAL The Flash memory organization is shown as Figure 6 4 2 User Configuration Application Program Memory ISP Loader Program Memory 0x0000_0000 0x0010_0000 Reserved for Further Used 0x000...

Page 146: ...SC10K after chip powered on 1 Watchdog Timer Disabled after chip powered on 30 CWDTPDEN Watchdog Clock Power down Enable Bit 0 OSC10K Watchdog Timer clock source is forced to be always enabled 1 OSC10...

Page 147: ...Reserved Reserved 1 LOCK Security Lock 0 Flash data is locked 1 Flash data is not locked When flash data is locked only device ID CONFIG0 and CONFIG1 can be read by writer and ICP through serial debu...

Page 148: ...DFBADR 15 DFBADR 14 DFBADR 13 DFBADR 12 DFBADR 11 DFBADR 10 DFBADR 9 DFBADR 8 7 6 5 4 3 2 1 0 DFBADR 7 DFBADR 6 DFBADR 5 DFBADR 4 DFBADR 3 DFBADR 2 DFBADR 1 DFBADR 0 Config Address 0x0030_0004 Bits De...

Page 149: ...execute code in APROM and call the functions in LDROM or to execute code in LDROM and call the APROM function without changing boot mode CBS 0 needs to be set as 0 and this is called In Application Pr...

Page 150: ...ISP The NuMicro NUC029LEE NUC029SEE supports ISP mode which allows a device to be reprogrammed under software control and avoids system fail risk when download or programming fail Furthermore the capa...

Page 151: ...r needs to set the ISPCON control register to decide to update LDROM User Configuration APROM and enable ISP controller Once the ISPCON register is set properly user can set ISPCMD for erase read or p...

Page 152: ...ation is finished or not by the ISPGO bit User should add ISB instruction next to the instruction in which ISPGO bit is set 1 to ensure correct execution of the instructions following ISP operation En...

Page 153: ...memory origination It must be 512 bytes page alignment N A FLASH Program 0x21 Valid address of flash memory origination Programming Data FLASH Read 0x00 Valid address of flash memory origination Retu...

Page 154: ...MC_BA 0x5000_C000 ISPCON FMC_BA 0x00 R W ISP Control Register 0x0000_0000 ISPADR FMC_BA 0x04 R W ISP Address Register 0x0000_0000 ISPDAT FMC_BA 0x08 R W ISP Data Register 0x0000_0000 ISPCMD FMC_BA 0x0...

Page 155: ...te Protect This bit is set by hardware when a triggered ISP meets any of the following conditions 1 APROM writes to itself if APUEN is set to 0 2 LDROM writes to itself if LDUEN is set to 0 3 CONFIG i...

Page 156: ...ctively This bit also functions as chip booting status flag which can be used to check where chip booted from This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happene...

Page 157: ...R W Description Reset Value ISPADR FMC_BA 0x04 R W ISP Address Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPADR 23 22 21 20 19 18 17 16 ISPADR 15 14 13 12 11 10 9 8 ISPADR 7 6 5 4 3 2 1 0 ISPADR B...

Page 158: ...er ISPDAT Register Offset R W Description Reset Value ISPDAT FMC_BA 0x08 R W ISP Data Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT 23 22 21 20 19 18 17 16 ISPDAT 15 14 13 12 11 10 9 8 ISPDAT 7...

Page 159: ...ion Reset Value ISPCMD FMC_BA 0x0C R W ISP Command Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPCMD...

Page 160: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPGO Bits Description 31 1 Reserved Reserved 0 ISPGO ISP Start Trigger Write Protection Bit Write 1 to start ISP ope...

Page 161: ...ion Reset Value DFBADR FMC_BA 0x14 R Data Flash Base Address 0x000X_XXXX 31 30 29 28 27 26 25 24 DFBADR 23 22 21 20 19 18 17 16 DFBADR 15 14 13 12 11 10 9 8 DFBADR 7 6 5 4 3 2 1 0 DFBADR Bits Descript...

Page 162: ...rved 6 FOMSEL1 Chip Frequency Optimization Mode Select1 Write protection Bit 5 Reserved Reserved 4 FOMSEL0 Chip Frequency Optimization Mode Select 0 Write Protection Bit When CPU frequency is lower th...

Page 163: ...to address VECMAP 11 0 9 h000 VECMAP 11 0 9 h1FF 8 7 Reserved Reserved 6 ISPFF ISP Fail Flag Write Protection Bit This bit is set by hardware when a triggered ISP meets any of the following condition...

Page 164: ...e And address latch enable ALE signal is used to differentiate the address and data cycle 6 5 2 Features External Bus Interface has the following functions Supports external devices with max 64 KB siz...

Page 165: ...ss hits EBI s memory space the corresponding EBI chip select signal nCS is assert and EBI state machine operates For an 8 bit device 64 Kbytes EBI mapped this 64 Kbytes device to 0x6000_0000 0x6000_FF...

Page 166: ...evice Addr 7 0 nCS nOE Data 7 0 nWE nCS nRE AD 7 0 nWE External Bus Interface 64K x 8 bit SRAM Address latch device ALE AD 7 0 En D Q AD 7 0 AD 15 8 Addr 15 8 Figure 6 5 3 Connection of 8 bit EBI Data...

Page 167: ...ts to low when write access Then nRD or nWR signal asserts to high after keeps access time tACC for reading output stable or writing finish After that EBI signals keep for data access hold time tAHD a...

Page 168: ...ess output 15 0 Figure 6 5 4 Timing Control Waveform for 16 bit Data Width The figure above shows an example of setting 16 bit data width for EBI application In this example AD0 AD15 are used to be ad...

Page 169: ...0 WData output 7 0 RData input Address output 7 0 AD 15 8 Address output 15 8 AD 15 8 Address output 15 8 Figure 6 5 5 Timing Control Waveform for 8 bit Data Width The figure above shows an example o...

Page 170: ...signals of EBI bus are inactive The following figure shows idle cycle nCS AD 15 0 MCLK nRD tACC tASU tAHD nWR AD 15 0 ALE tALE tLHD tA2D Address output 15 0 WData output 15 0 RData input Idle cycle X...

Page 171: ...ead only W write only R W both read and write Register Offset R W Description Reset Value EBI Base Address EBI_BA 0x5001_0000 EBICON EBI_BA 0x00 R W External Bus Interface General Control Register 0x0...

Page 172: ...rved ExttALE 15 14 13 12 11 10 9 8 Reserved MCLKDIV 7 6 5 4 3 2 1 0 Reserved ExtBW16 ExtEN Bits Description 31 19 Reserved Reserved 18 16 ExttALE Expand Time of ALE This field is used for control the...

Page 173: ...497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL This bit defines if the data bus is 8 bit or 16 bit 1 EBI data width is 16 bit 0 EBI data width is 8 bit 0 ExtEN EBI Enable This bi...

Page 174: ...escription 31 28 Reserved Reserved 27 24 ExtIR2R Idle State Cycle Between Read Read When read action is finished and the next action is going to read idle state is inserted and nCS signal return to hi...

Page 175: ...7 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WAHD_OFF RAHD_OFF WBUFF_EN Bits Description 31 3 Reserved Reserved 2 WAHD_OFF Access Hold T...

Page 176: ...lly as input output open drain or Quasi bidirectional mode After reset the I O mode of all pins are depending on Config0 10 setting In Quasi bidirectional mode I O pin has a very weak individual pull...

Page 177: ...PMDn 1 0 to 00b as the GPIOx port n pin is in Input mode and the I O pin is in tri state high impedance without output drive capability The GPIOx_PIN value reflects the status of the corresponding po...

Page 178: ...n is in Quasi bidirectional mode and the I O pin supports digital output and input function at the same time but the source current is only up to hundreds of uA Before the digital input function is pe...

Page 179: ...ter The GPIO can also be the chip wake up source when chip enters Idle mode or Power down mode The setting of wake up trigger condition is the same as GPIO interrupt trigger but there is one thing nee...

Page 180: ...n I O Mode Control Register 0xXXXX_XXXX GPIOB_OFFD GPIO_BA 0x044 R W GPIO Port B Pin Digital Input Path Disable Control Register 0x0000_0000 GPIOB_DOUT GPIO_BA 0x048 R W GPIO Port B Data Output Value...

Page 181: ...Register 0x0000_0000 GPIOE_IMD GPIO_BA 0x118 R W GPIO Port E Interrupt Mode Control Register 0x0000_0000 GPIOE_IEN GPIO_BA 0x11C R W GPIO Port E Interrupt Enable Register 0x0000_0000 GPIOE_ISRC GPIO_...

Page 182: ...1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL Register Offset R W Description Reset Value PEn_PDIO n 0 1 15 GPIO_BA 0x300 0x04 n R W GPIO PE n Pin Data Input Output Register 0x0000_000X...

Page 183: ...0 29 28 27 26 25 24 PMD15 PMD14 PMD13 PMD12 23 22 21 20 19 18 17 16 PMD11 PMD10 PMD9 PMD8 15 14 13 12 11 10 9 8 PMD7 PMD6 PMD5 PMD4 7 6 5 4 3 2 1 0 PMD3 PMD2 PMD1 PMD0 Bits Description 2n 1 2n n 0 1 1...

Page 184: ...PIO Port E Pin Digital Input Path Disable Register 0x0000_0000 GPIOF_OFFD GPIO_BA 0x144 R W GPIO Port F Pin Digital Input Path Disable Register 0x0000_0000 31 30 29 28 27 26 25 24 OFFD 23 22 21 20 19...

Page 185: ...x148 R W GPIO Port F Data Output Value Register 0x0000_000F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DOUT 7 6 5 4 3 2 1 0 DOUT Bits Description 31 16 Res...

Page 186: ...Mask Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DMASK 7 6 5 4 3 2 1 0 DMASK Bits Description 31 16 Reserved Reserved n n 0 1 15 DMASK...

Page 187: ...X GPIOE_PIN GPIO_BA 0x110 R GPIO Port E Pin Value 0x0000_XXXX GPIOF_PIN GPIO_BA 0x150 R GPIO Port F Pin Value 0x0000_000X 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 188: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DBEN 7 6 5 4 3 2 1 0 DBEN Bits Description 31 16 Reserved Reserved n n 0 1 15 DBEN n Port A B C E F Input Signal De Bounce Enable Bit DBEN n is used to enab...

Page 189: ...14 13 12 11 10 9 8 IMD 7 6 5 4 3 2 1 0 IMD Bits Description 31 16 Reserved Reserved n n 0 1 15 IMD n Port A B C E F Edge Or Level Detection Interrupt Control IMD n is used to control the interrupt is...

Page 190: ...so enable the pin wake up function When setting the IR_EN n bit to 1 If the interrupt is level trigger the input PIN n state at level high will generate the interrupt If the interrupt is edge trigger...

Page 191: ...O_BA 0x0A0 R W GPIO Port C Interrupt Source Flag Register 0x0000_0000 GPIOE_ISRC GPIO_BA 0x120 R W GPIO Port E Interrupt Source Flag Register 0x0000_0000 GPIOF_ISRC GPIO_BA 0x160 R W GPIO Port F Inter...

Page 192: ...ter reset It is recommended to disable this bit to save system power if no special application concern 4 DBCLKSRC De Bounce Counter Clock Source Selection 0 De bounce counter clock source is the HCLK...

Page 193: ...age 193 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 12 Sample interrupt input once per 16 256 clocks 13 Sample interrupt input once per 32 256 clocks 14 Sample interrupt inp...

Page 194: ...gister 0x0000_000X PFn_PDIO n 0 1 GPIO_BA 0x340 0x04 n R W GPIO PF n Pin Data Input Output Register 0x0000_000X Note x A B C E F and n 0 15 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Res...

Page 195: ...can perform CRC calculation with programmable polynomial settings The CRC engine supports CPU PIO mode and DMA transfer mode 6 7 2 Features Supports nine PDMA channels and one CRC channel Each PDMA c...

Page 196: ...bit write mode word 4 AHB clock cycle operation Supports byte alignment transfer data length and word alignment transfer source address in CRC DMA mode 6 7 3 Block Diagram AHB Bus Interface SPI0 SPI1...

Page 197: ...generator channel The CPU can recognize the completion of a DMA operation by software polling or when it receives an internal DMA interrupt 6 7 5 1 PDMA The DMA controller has nine channels PDMA Peri...

Page 198: ...EN PDMA_CSRx 23 bits field to start again In PDMA Peripheral to Memory or Memory to Peripheral mode DMA can transfer data between the Peripherals e g UART SPI ADC and Memory 6 7 5 2 CRC The DMA contro...

Page 199: ...24 checksum reverse CHECKSUM_RVS CRC_CTL 25 write data 1 s complement WDATA_COM CRC_CTL 26 checksum 1 s complement CHECKSUM_COM CRC_CTL 27 and initial seed value in CRC seed register CRC_SEED CRC_SEE...

Page 200: ...000 PDMA_CSARx x 0 1 8 PDMA_CHx_BA 0x14 R PDMA Channel x Current Source Address Register 0x0000_0000 PDMA_CDARx x 0 1 8 PDMA_CHx_BA 0x18 R PDMA Channel x Current Destination Address Register 0x0000_00...

Page 201: ...Register 0x0000_0000 CRC_SEED CRC_BA 0x84 R W CRC Seed Register 0xFFFF_FFFF CRC_CHECKSUM CRC_BA 0x88 R CRC Checksum Register 0xFFFF_FFFF PDMA_GCRCSR PDMA_GCR_BA 0x00 R W PDMA Global Control Register...

Page 202: ...s bit will be cleared automatically If the bus error occurs all PDMA transfer will be stopped Software must reset all PDMA channel and then trigger again 22 21 Reserved Reserved 20 19 APB_TWS Peripher...

Page 203: ...d 3 2 MODE_SEL PDMA Mode Selection 00 Memory to Memory mode Memory to Memory 01 Peripheral to Memory mode Peripheral to Memory 10 Memory to Peripheral mode Memory to Peripheral 1 SW_RST Software Engin...

Page 204: ...fset R W Description Reset Value PDMA_SARx x 0 1 8 PDMA_CHx_BA 0x04 R W PDMA Channel x Source Address Register 0x0000_0000 31 30 29 28 27 26 25 24 PDMA_SAR 23 22 21 20 19 18 17 16 PDMA_SAR 15 14 13 12...

Page 205: ...W Description Reset Value PDMA_DARx x 0 1 8 PDMA_CHx_BA 0x08 R W PDMA Channel x Destination Address Register 0x0000_0000 31 30 29 28 27 26 25 24 PDMA_DAR 23 22 21 20 19 18 17 16 PDMA_DAR 15 14 13 12 1...

Page 206: ...R W Description Reset Value PDMA_BCRx x 0 1 8 PDMA_CHx_BA 0x0C R W PDMA Channel x Transfer Byte Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 207: ...r Offset R W Description Reset Value PDMA_POINTx x 0 1 8 PDMA_CHx_BA 0x10 R PDMA Channel x Internal Buffer Pointer Register 0xXXXX_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserve...

Page 208: ...er Offset R W Description Reset Value PDMA_CSARx x 0 1 8 PDMA_CHx_BA 0x14 R PDMA Channel x Current Source Address Register 0x0000_0000 31 30 29 28 27 26 25 24 PDMA_CSAR 23 22 21 20 19 18 17 16 PDMA_CS...

Page 209: ...fset R W Description Reset Value PDMA_CDARx x 0 1 8 PDMA_CHx_BA 0x18 R PDMA Channel x Current Destination Address Register 0x0000_0000 31 30 29 28 27 26 25 24 PDMA_CDAR 23 22 21 20 19 18 17 16 PDMA_CD...

Page 210: ...x x 0 1 8 PDMA_CHx_BA 0x1C R PDMA Channel x Current Transfer Byte Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PDMA_CBCR 7 6 5 4 3...

Page 211: ...1 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BLKD_IE TABORT_IE Bits Description 31 2 Reserved Reserved 1 BLKD_IE PDMA Block...

Page 212: ...Bits Description 31 2 Reserved Reserved 1 BLKD_IF PDMA Block Transfer Done Interrupt Flag This bit indicates that PDMA has finished all transfers 0 Not finished 1 Done Write 1 to clear this bit to 0...

Page 213: ...UF0_Cx Register Offset R W Description Reset Value PDMA_SBUF0_Cx x 0 1 8 PDMA_CHx_BA 0x80 R PDMA Channel x Shared Buffer FIFO 0 Register 0x0000_0000 31 30 29 28 27 26 25 24 PDMA_SBUF0 23 22 21 20 19 1...

Page 214: ...s field indicates the CPU write data length only when operating in CPU PIO mode 00 The write data length is 8 bit mode 01 The write data length is 16 bit mode 10 The write data length is 32 bit mode 1...

Page 215: ...n CRC DMA mode do not fill in any data in CRC_WDATA register Note2 When CRC DMA transfer completed this bit will be cleared automatically Note3 If the bus error occurs when CRC DMA transfer data all C...

Page 216: ...et Value CRC_DMASAR CRC_BA 0x04 R W CRC DMA Source Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CRC_DMASAR 23 22 21 20 19 18 17 16 CRC_DMASAR 15 14 13 12 11 10 9 8 CRC_DMASAR 7 6 5 4 3 2 1 0 C...

Page 217: ...on Reset Value CRC_DMABCR CRC_BA 0x0C R W CRC DMA Transfer Byte Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CRC_DMABCR 7 6 5 4 3...

Page 218: ...eset Value CRC_DMACSAR CRC_BA 0x14 R CRC DMA Current Source Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CRC_DMACSAR 23 22 21 20 19 18 17 16 CRC_DMACSAR 15 14 13 12 11 10 9 8 CRC_DMACSAR 7 6 5...

Page 219: ...CRC DMA Current Transfer Byte Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CRC_DMACBCR 7 6 5 4 3 2 1 0 CRC_DMACBCR Bits Descripti...

Page 220: ...Bits Description 31 2 Reserved Reserved 1 CRC_BLKD_IE CRC DMA Block Transfer Done Interrupt Enable Bit Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF CRC_D...

Page 221: ..._CTL 23 bit has enabled 1 CRC transfer done if TRIG_EN CRC_CTL 23 bit has enabled It is cleared by writing 1 to it through software When CRC DMA transfer done TRIG_EN CRC_CTL 23 bit will be cleared au...

Page 222: ...19 18 17 16 CRC_WDATA 15 14 13 12 11 10 9 8 CRC_WDATA 7 6 5 4 3 2 1 0 CRC_WDATA Bits Description 31 0 CRC_WDATA CRC Write Data Register When operating in CPU PIO mode software can write data to this f...

Page 223: ...E MANUAL CRC Seed Register CRC_SEED Register Offset R W Description Reset Value CRC_SEED CRC_BA 0x84 R W CRC Seed Register 0xFFFF_FFFF 31 30 29 28 27 26 25 24 CRC_SEED 23 22 21 20 19 18 17 16 CRC_SEED...

Page 224: ...Register CRC_CHECKSUM Register Offset R W Description Reset Value CRC_CHECKSUM CRC_BA 0x88 R CRC Checksum Register 0xFFFF_FFFF 31 30 29 28 27 26 25 24 CRC_CHECKSUM 23 22 21 20 19 18 17 16 CRC_CHECKSUM...

Page 225: ...LK4_EN CLK3_EN CLK2_EN CLK1_EN CLK0_EN 7 6 5 4 3 2 1 0 Reserved Bits Description 31 25 Reserved Reserved 24 CRC_CLK_EN CRC Controller Clock Enable Bit 0 Disabled 1 Enabled 23 17 Reserved Reserved 16 C...

Page 226: ...NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 10 CLK2_EN PDMA Controller Channel 2 Clock Enable Bit 0 Disabled 1 Enabled 9 CLK1_EN PDMA Controller Channel 1 Clock Enable Bit 0 Disabled 1 Enab...

Page 227: ...he explanation of SPI0_RXSEL PDMA_PDSSR0 3 0 23 20 SPI2_TXSEL PDMA SPI2 TX Selection This field defines which PDMA channel is connected to the on chip peripheral SPI2 TX Software can configure the TX...

Page 228: ...ing by this field The channel configuration is the same as SPI0_RXSEL PDMA_PDSSR0 3 0 field Please refer to the explanation of SPI0_RXSEL PDMA_PDSSR0 3 0 3 0 SPI0_RXSEL PDMA SPI0 RX Selection This fie...

Page 229: ...of UART0_RXSEL PDMA_PDSSR1 3 0 23 16 Reserved Reserved 15 12 UART1_TXSEL PDMA UART1 TX Selection This field defines which PDMA channel is connected to the on chip peripheral UART1 TX Software can con...

Page 230: ...0_RXSEL PDMA UART0 RX Selection This field defines which PDMA channel is connected to the on chip peripheral UART0 RX Software can change the channel RX setting by this field For example UART0_RXSEL P...

Page 231: ...DMA controller Note This bit is read only 30 17 Reserved Reserved 16 INTRCRC Interrupt Status Of CRC Controller This bit is the interrupt status of CRC controller Note This bit is read only 15 9 Reser...

Page 232: ...interrupt status of PDMA channel3 Note This bit is read only 2 INTR2 Interrupt Status Of Channel 2 This bit is the interrupt status of PDMA channel2 Note This bit is read only 1 INTR1 Interrupt Statu...

Page 233: ...32 bit timers with 24 bit up counter and one 8 bit prescale counter Independent clock source for each timer Provides four timer counting modes one shot periodic toggle and continuous counting Time ou...

Page 234: ...upt TM0 TM3 Internal 24 bit up counter 8 bit pre scale 0 1 CTB TCSR 24 TMRx_CLK CEN TCSR 30 CRST TCSR 26 0 1 TX_PHASE TEXCON 0 Reset counter 24 bit TDR TDR 23 0 24 bit TCMPR 23 0 TIF TISR 0 Reset coun...

Page 235: ...e 111 010 001 HCLK 32 768 kHz LXT 4 24 MHz HXT TMR0_S CLKSEL1 10 8 TMR1_S CLKSEL1 14 12 TMR2_S CLKSEL1 18 16 TMR3_S CLKSEL1 22 20 TMR0_EN APBCLK 2 TMR1_EN APBCLK 3 TMR2_EN APBCLK 4 TMR3_EN APBCLK 5 TM...

Page 236: ...ed by timer controller then timer counting operation stops In the meantime if the IE TCSR 29 bit is enabled the timer interrupt signal is generated and sent to NVIC to inform CPU also 6 8 5 3 Periodic...

Page 237: ...set as 80 first The TIF flag will set to 1 when TDR value is equal to 80 timer counter is kept counting and TDR value will not goes back to 0 it continues to count 81 82 83 to 2 24 1 0 1 2 3 to 2 24 1...

Page 238: ...Mode The event capture function is used to capture Timer Capture Data Register TDR value to TCAP value while edge transition detected on TMx_EXT pin x 0 3 In this mode RSTCAPSEL TEXCON 4 bit should be...

Page 239: ...mer1 Compare Register 0x0000_0000 TISR1 TMR01_BA 0x28 R W Timer1 Interrupt Status Register 0x0000_0000 TDR1 TMR01_BA 0x2C R Timer1 Data Register 0x0000_0000 TCAP1 TMR01_BA 0x30 R Timer1 Capture Data R...

Page 240: ...f 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL TCAP3 TMR23_BA 0x30 R Timer3 Capture Data Register 0x0000_0000 TEXCON3 TMR23_BA 0x34 R W Timer3 External Control Register 0x0000_0...

Page 241: ...6 5 4 3 2 1 0 PRESCALE Bits Description 31 DBGACK_TMR ICE Debug Mode Acknowledge Disable Bit Write Protect 0 ICE debug mode acknowledgement effects TIMER counting TIMER counter will be held while CPU...

Page 242: ...unter Mode Enable Bit This bit is for external counting pin function enabled When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source Please refer to 6...

Page 243: ...11 10 9 8 TCMP 7 6 5 4 3 2 1 0 TCMP Bits Description 31 24 Reserved Reserved 23 0 TCMP Timer Compared Value TCMP is a 24 bit compared value register When the internal 24 bit up counter value is equal...

Page 244: ...Interrupt Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TWF TIF Bits Description 31 2 Reserved...

Page 245: ...er 0x0000_0000 TDR1 TMR01_BA 0x2C R Timer1 Data Register 0x0000_0000 TDR2 TMR23_BA 0x0C R Timer2 Data Register 0x0000_0000 TDR3 TMR23_BA 0x2C R Timer3 Data Register 0x0000_0000 31 30 29 28 27 26 25 24...

Page 246: ...01_BA 0x30 R Timer1 Capture Data Register 0x0000_0000 TCAP2 TMR23_BA 0x10 R Timer2 Capture Data Register 0x0000_0000 TCAP3 TMR23_BA 0x30 R Timer3 Capture Data Register 0x0000_0000 31 30 29 28 27 26 25...

Page 247: ...x pin de bounce Disabled 1 TMx pin de bounce Enabled If this bit is enabled the edge detection of TMx pin is detected with de bounce circuit 6 TEXDB Timer External Capture Input Pin De Bounce Enable B...

Page 248: ...EX_EDGE Timer External Capture Pin Edge Detect Selection 00 A 1 to 0 transition on TMx_EXT pin will be detected 01 A 0 to 1 transition on TMx_EXT pin will be detected 10 Either 1 to 0 or 0 to 1 transi...

Page 249: ...er 0x0000_0000 TEXISR3 TMR23_BA 0x38 R W Timer3 External Interrupt Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4...

Page 250: ...ture avoids glitch at PWM outputs When the 16 bit period down counter reaches 0 the interrupt request is generated If PWM timer is set as auto reload mode when the down counter reaches 0 it is reloade...

Page 251: ...ry PWM paired channels PWM group A has two PWM generators and PWM group B has one PWM generator with each PWM generator supporting one 8 bit prescaler two clock dividers two PWM timers one Dead zone g...

Page 252: ...1_S CLKSEL2 8 CLKSEL1 29 28 PWM01_EN APBCLK 20 PWM01_CLK 111 10 kHz Figure 6 9 1 PWM Generator 0 Clock Source Control CSR1 CSR 6 4 100 000 1 1 2 1 4 1 8 1 16 001 010 011 100 000 1 1 2 1 4 1 8 1 16 001...

Page 253: ...1 2 1 4 1 8 1 16 001 010 011 100 000 1 1 2 1 4 1 8 1 16 001 010 011 CSR2 CSR 10 8 8 bit Prescaler PWM Timer2 Logic CNR2 CMR2 PCR PWM Timer3 Logic 1 0 Dead Zone Generator 2 DZI23 PPR 31 24 DZEN23 PCR...

Page 254: ...1 1 2 1 4 1 8 1 16 001 010 011 100 000 1 1 2 1 4 1 8 1 16 001 010 011 CSR0 CSR 2 0 8 bit Prescaler PWM Timer0 Logic CNR0 CMR0 PCR PWM Timer1 Logic 1 0 Dead Zone Generator 0 DZI01 PPR 23 16 DZEN01 PCR...

Page 255: ...t to high and CMRn new and CNRn new are updated with CHnMODE 1 and request the PWM interrupt if PWM interrupt is enabled PWMIEn PIER 3 0 1 The PWM period and duty control are configured by PWM down co...

Page 256: ...1 CMR 1 CNR 3 Auto reload 1 CHnMOD 1 Set CHnEN 1 PWM Timer starts running CMR 0 CNR 4 Auto load S W write new value Auto load Write initial setting H W update value PWMIFn is set by H W PWMIFn is set...

Page 257: ...IER 17 16 0 i e at start end of each PWM cycle or at up counter matching with CNRn if INTxxTYPE PIER 17 16 1 i e at center point of PWM cycle PWM frequency PWMxy_CLK prescale 1 clock divider CNR 1 whe...

Page 258: ...t switch PWM0 operating mode before set CH0EN PCR 0 bit to 1 to enable PWM0 counter start running because the content of CNR0 and CMR0 will be cleared to 0 to reset the PWM0 period and duty setting wh...

Page 259: ...Ratio The double buffering function allows CMRn written at any point in current cycle The loaded value will take effect from next cycle Modulate PWM controller ouput duty ratio CNR 150 Write CMR 100...

Page 260: ...PWM period Figure 6 9 15 PWM trigger ADC to conversion in Center aligned type Timing Waveform 6 9 5 8 Capture Operation The Capture 0 and PWM 0 share one timer that included in PWM 0 and the Capture...

Page 261: ...No reload due to no CAPIFn Figure 6 9 16 Capture Operation Timing In this case the CNR is 8 The PWM counter will be reloaded with CNRn when a capture interrupt flag CAPIFn is set The channel low puls...

Page 262: ..._INT PWMIF1 CAPIF1 PWM2_INT PWMIF2 CAPIF2 PWM3_INT PWMIF3 CAPIF3 PWMA_INT PWMDIF0 PWMDIF1 PWMDIF2 PWMDIF3 PWM Interrupt source in PWMA group Figure 6 9 17 PWM Group A PWM Timer Interrupt Architecture...

Page 263: ...ble POE and disable CAPENR for the corresponding PWM channel 12 Enable PWM timer start running Set CHnEN 1 in PCR 6 9 5 11Modify PWM counter register CNR comparator register CMR Clock prescaler CP01 C...

Page 264: ...al and lead to change the duty of the PWM output this may cause damage to the control circuit of motor 6 9 5 14Capture Start Procedure 1 Setup clock source divider select register CSR 2 Wait until SYN...

Page 265: ...PWM Comparator Register 0 0x0000_0000 PDR0 PWMA_BA 0x14 PWMB_BA 0x14 R PWM Data Register 0 0x0000_0000 CNR1 PWMA_BA 0x18 PWMB_BA 0x18 R W PWM Counter Register 1 0x0000_0000 CMR1 PWMA_BA 0x1C PWMB_BA...

Page 266: ...Register Channel 2 0x0000_0000 CFLR2 PWMA_BA 0x6C R PWM Capture Falling Latch Register Channel 2 0x0000_0000 CRLR3 PWMA_BA 0x70 R PWM Capture Rising Latch Register Channel 3 0x0000_0000 CFLR3 PWMA_BA...

Page 267: ...r PWM23_CLK 23 16 DZI01 Dead Zone Interval For Pair Of Channel 0 And Channel 1 PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B These 8 bit determine the Dead zone length The unit...

Page 268: ...d Reserved 14 12 CSR3 PWM Timer 3 Clock Source Divider Selection PWM Timer 3 For Group A Select clock source divider for PWM timer 3 000 2 001 4 010 8 011 16 100 1 11 Reserved Reserved 10 8 CSR2 PWM T...

Page 269: ...nter aligned type 30 PWM01TYPE PWM01 Aligned Type Selection PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B 0 Edge aligned type 1 Center aligned type 30 28 Reserved Reserved 27 C...

Page 270: ...PWM Timer 5 For Group B 0 Inverter Disable 1 Inverter Enable 9 CH1PINV PWM Timer 1 Output Polar Inverse Enable PWM Timer 1 For Group A And PWM Timer 5 For Group B 0 PWM1 output polar inverse Disabled...

Page 271: ...oup A And PWM Timer 4 For Group B 0 Inverter Disabled 1 Inverter Enabled 1 CH0PINV PWM Timer 0 Output Polar Inverse Enable PWM Timer 0 For Group A And PWM Timer 4 For Group B 0 PWM0 output polar inver...

Page 272: ...Loaded Value CNR determines the PWM period PWM frequency PWMxy_CLK prescale 1 clock divider CNR 1 where xy could be 01 23 or 45 depends on selected PWM channel For Edge aligned type Duty ratio CMR 1 C...

Page 273: ...ved 15 14 13 12 11 10 9 8 CMRx 7 6 5 4 3 2 1 0 CMRx Bits Description 31 16 Reserved Reserved 15 0 CMRx PWM Comparator Register CMR determines the PWM duty PWM frequency PWMxy_CLK prescale 1 clock divi...

Page 274: ...0x14 R PWM Data Register 0 0x0000_0000 PDR1 PWMA_BA 0x20 PWMB_BA 0x20 R PWM Data Register 1 0x0000_0000 PDR2 PWMA_BA 0x2C R PWM Data Register 2 0x0000_0000 PDR3 PWMA_BA 0x38 R PWM Data Register 3 0x00...

Page 275: ...ter 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BCn Bits Description 31 1 Reserved Reserved 0 BCn PWM Backward...

Page 276: ...t PWM2 And PWM3 Pair For PWM Group A 0 PWMIFn will be set if PWM counter underflow 1 PWMIFn will be set if PWM counter matches CNRn register Note This bit is effective when PWM in Center aligned type...

Page 277: ...29SEE TECHNICAL REFERENCE MANUAL 3 PWMIE3 PWM Channel 3 Period Interrupt Enable Bit 0 Disabled 1 Enabled 2 PWMIE2 PWM Channel 2 Period Interrupt Enable Bit 0 Disabled 1 Enabled 1 PWMIE1 PWM Channel 1...

Page 278: ...Note If CMR equal to CNR this flag is not working in Edge aligned type selection 9 PWMDIF1 PWM Channel 1 Duty Interrupt Flag Flag is set by hardware when channel 1 PWM counter down count and reaches C...

Page 279: ...1TYPE bit of PIER register software can write 1 to clear this bit to 0 0 PWMIF0 PWM Channel 0 Period Interrupt Status This bit is set by hardware when PWM0 counter reaches the requirement of interrupt...

Page 280: ...Indicator Bit When PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down counter and this bit is set by hardware Software can write 0 to clear this bit to 0 i...

Page 281: ...e can write 0 to clear this bit to 0 if the BCn bit is 0 and can write 1 to clear this bit to 0 if the BCn bit is 1 5 Reserved Reserved 4 CAPIF0 Channel 0 Capture Interrupt Indication Flag If PWM grou...

Page 282: ...NUC029SEE 32 bit Arm Cortex M0 Microcontroller Aug 2018 Page 282 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 1 Inverter Enabled Reverse the input signal from GPIO before fed...

Page 283: ...p input channel 3 has a rising transition CRLR3 was latched with the value of PWM down counter and this bit is set by hardware Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can w...

Page 284: ...can write 1 to clear this bit to 0 if the BCn bit is 1 5 Reserved Reserved 4 CAPIF2 Channel 2 Capture Interrupt Indication Flag If PWM group channel 2 rising latch interrupt is enabled CRL_IE2 1 a ri...

Page 285: ...000_0000 CRLR1 PWMA_BA 0x60 PWMB_BA 0x60 R PWM Capture Rising Latch Register Channel 1 0x0000_0000 CRLR2 PWMA_BA 0x68 R PWM Capture Rising Latch Register Channel 2 0x0000_0000 CRLR3 PWMA_BA 0x70 R PWM...

Page 286: ...0000_0000 CFLR1 PWMA_BA 0x64 PWMB_BA 0x64 R PWM Capture Falling Latch Register Channel 1 0x0000_0000 CFLR2 PWMA_BA 0x6C R PWM Capture Falling Latch Register Channel 2 0x0000_0000 CFLR3 PWMA_BA 0x74 R...

Page 287: ...PIO multi function is set as PWM3 2 CINEN2 Channel 2 Capture Input Enable Bit 0 PWM Channel 2 capture input path Disabled The input of PWM channel 2 capture function is always regarded as 0 1 PWM Chan...

Page 288: ...utput Enable Bit 0 PWM channel 3 output to pin Disabled 1 PWM channel 3 output to pin Enabled Note The corresponding GPIO pin must also be switched to PWM function 2 POE2 Channel 2 Output Enable Bit 0...

Page 289: ...operating at Center aligned type 2 PWM2TEN Channel 2 Center Aligned Trigger Enable Bit 0 PWM channel 2 trigger ADC function Disabled 1 PWM channel 2 trigger ADC function Enabled PWM can trigger ADC t...

Page 290: ...can write 1 to clear this bit 2 PWM2TF Channel 2 Center Aligned Trigger Flag For Center aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set t...

Page 291: ...4 3 2 1 0 Reserved S_BUSY Bits Description 31 1 Reserved Reserved 0 S_BUSY PWM Synchronous Busy When software writes CNR0 CMR0 PPR or switches PWM0 operation mode PCR 3 PWM will have a busy time to u...

Page 292: ...4 3 2 1 0 Reserved S_BUSY Bits Description 31 1 Reserved Reserved 0 S_BUSY PWM Synchronous Busy When Software writes CNR1 CMR1 PPR or switches PWM1 operation mode PCR 11 PWM will have a busy time to u...

Page 293: ...1 0 Reserved S_BUSY Bits Description 31 1 Reserved Reserved 0 S_BUSY PWM Synchronous Busy When Software writes CNR2 CMR2 PPR or switch PWM2 operation mode PCR 19 PWM will have a busy time to update t...

Page 294: ...2 1 0 Reserved S_BUSY Bits Description 31 1 Reserved Reserved 0 S_BUSY PWM Synchronous Busy When Software writes CNR3 CMR3 PPR or switch PWM3 operation mode PCR 27 PWM will have a busy time to update...

Page 295: ...from Idle Power down mode 6 10 2 Features 18 bit free running up counter for Watchdog Timer time out interval Selectable time out interval 2 4 2 18 WDT_CLK cycle and the time out interval period is 1...

Page 296: ...LIRC Low Speed Internal clock signal Figure 6 10 1 Watchdog Timer Clock Control Internal 18 bit WDT Up Counter 0 15 4 16 17 000 001 110 111 WDT_CLK Time out Interval Period Select Reset Delay Select W...

Page 297: ...ting to 1 User should set WTR bit to reset the 18 bit WDT up counter value to avoid generate WDT time out reset signal before the TRSTD delay period expires If the WDT up counter value has not been cl...

Page 298: ...TWDT Table 6 10 1 Watchdog Timer Time out Interval Period Selection TTIS WDT reset low reset TRSTD TRST TWDT TWDT Watchdog Clock Time Period TTIS Watchdog Timeout Interval Period 24 218 TWDT TRSTD Wat...

Page 299: ...EE TECHNICAL REFERENCE MANUAL 6 10 6 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0x4000_4000 WTCR WDT_BA 0x00 R W...

Page 300: ...edge Disable Bit Write Protect 0 ICE debug mode acknowledgement effects WDT counting WDT up counter will be held while CPU is held by ICE 1 ICE debug mode acknowledgement Disabled WDT up counter will...

Page 301: ...1 Wake up trigger event Enabled if WDT time out interrupt signal generated Note Chip can be woken up by WDT time out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillato...

Page 302: ...et Delay Selection Write Protect When WDT time out happened user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time out reset happened User can select a suitable value of...

Page 303: ...ammable maximum 11 bit prescale counter period of WWDT counter 6 11 3 Block Diagram The Window Watchdog Timer clock control and block diagram are shown as follows Note Before clock switching both the...

Page 304: ...Out Period Max Time Out Interval WWDT_CLK 10 KHz 0000 1 1 64 TWWDT 6 4 ms 0001 2 2 64 TWWDT 12 8 ms 0010 4 4 64 TWWDT 25 6 ms 0011 8 8 64 TWWDT 51 2 ms 0100 16 16 64 TWWDT 102 4 ms 0101 32 32 64 TWWD...

Page 305: ...1 by hardware WWDT Reset System When WWDTIF is generated user must reload WWDT internal counter value to 0x3F by writing 0x00005AA5 to WWDTRLD and also to prevent WWDT counter value reached to 0 and g...

Page 306: ...DT clocks to sync the reload command to actually perform reload action This means if user set PERIODSEL to 0000 the counter prescale value should be as 1 and the WINCMP value must be larger than 2 oth...

Page 307: ...read and write Register Offset R W Description Reset Value WWDT Base Address WWDT_BA 0x4000_4100 WWDTRLD WWDT_BA 0x00 W Window Watchdog Timer Reload Counter Register 0x0000_0000 WWDTCR WWDT_BA 0x04 R...

Page 308: ...eload Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 WWDTRLD 23 22 21 20 19 18 17 16 WWDTRLD 15 14 13 12 11 10 9 8 WWDTRLD 7 6 5 4 3 2 1 0 WWDTRLD Bits Description 31 0 WWDTRLD WWDT Reload Count...

Page 309: ...ed 21 16 WINCMP WWDT Window Compare Register Set this register to adjust the valid reload window Note User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0...

Page 310: ...1536 Max time out period is 1536 64 TWWDT 1111 Pre scale is 2048 Max time out period is 2048 64 TWWDT 7 2 Reserved Reserved 1 WWDTIE WWDT Interrupt Enable Bit If this bit is enabled the WWDT counter...

Page 311: ...served 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WWDTRF WWDTIF Bits Description 31 2 Reserved Reserved 1 WWDTRF WWDT Time Out Reset Flag This bit indicates the system has been reset by W...

Page 312: ...VR Register Offset R W Description Reset Value WWDTCVR WWDT_BA 0x0C R Window Watchdog Timer Counter Value Register 0x0000_003F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 1...

Page 313: ...alendar counter in Calendar Loading Register CLR year month day for RTC time and calendar check Supports alarm time hour minute second and calendar year month day settings in Time Alarm Register TAR a...

Page 314: ...R TSSR DWR Figure 6 12 1 RTC Block Diagram 6 12 4 Basic Configuration RTC controller clock enable is in RTC_EN APBCLK 1 and low speed 32 kHz oscillator is enabled by XTL32K_EN PWRCON 1 6 12 5 Function...

Page 315: ...TC control registers access attribute when ENF is 1 and 0 are shown in below table Register ENF 1 ENF 0 INIR R W R W AER R W R W FCR R W Not available TLR R W R CLR R W R TSSR R W R W DWR R W R TAR R...

Page 316: ...5 27 Hz 32768 Hz Integer part 32765 0x7FFD INTEGER FCR 11 8 Integer Part 0x0D 0x01 0x08 0x04 Fraction part 0 27 FRACTION FCR 5 0 Fraction Part 0 27 x 60 16 2 0x10 RTC FCR register should be as 0x410 6...

Page 317: ...ssage in TLR and CLR registers are equal to alarm time and calendar values in RTC TAR and CAR registers the AIF RIIR 0 RTC Alarm Interrupt Flag is set to 1 and the RTC alarm interrupt signal asserted...

Page 318: ...0x0000_0000 FCR RTC_BA 0x08 R W RTC Frequency Compensation Register 0x0000_0700 TLR RTC_BA 0x0C R W Time Loading Register 0x0000_0000 CLR RTC_BA 0x10 R W Calendar Loading Register 0x0005_0101 TSSR RT...

Page 319: ...RTC Spare Register 10 0x0000_0000 SPR11 RTC_BA 0x6C R W RTC Spare Register 11 0x0000_0000 SPR12 RTC_BA 0x70 R W RTC Spare Register 12 0x0000_0000 SPR13 RTC_BA 0x74 R W RTC Spare Register 13 0x0000_000...

Page 320: ...28 27 26 25 24 INIR 23 22 21 20 19 18 17 16 INIR 15 14 13 12 11 10 9 8 INIR 7 6 5 4 3 2 1 0 INIR Bits Description 31 1 INIR 31 1 RTC Initiation When RTC block is powered on RTC is at reset state User...

Page 321: ...eserved 23 22 21 20 19 18 17 16 Reserved ENF 15 14 13 12 11 10 9 8 AER 7 6 5 4 3 2 1 0 AER Bits Description 31 17 Reserved Reserved 16 ENF RTC Register Access Enable Flag Read Only 0 RTC register read...

Page 322: ...n Register 0x0000_0700 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved INTEGER 7 6 5 4 3 2 1 0 Reserved FRACTION Bits Description 31 12 Reserved Reserv...

Page 323: ...served 10MIN 1MIN 7 6 5 4 3 2 1 0 Reserved 10SEC 1SEC Bits Description 31 22 Reserved Reserved 21 20 10HR 10 Hour Time Digit 0 2 19 16 1HR 1 Hour Time Digit 0 9 15 Reserved Reserved 14 12 10MIN 10 Min...

Page 324: ...AR 1YEAR 15 14 13 12 11 10 9 8 Reserved 10MON 1MON 7 6 5 4 3 2 1 0 Reserved 10DAY 1DAY Bits Description 31 24 Reserved Reserved 23 20 10YEAR 10 Year Calendar Digit 0 9 19 16 1YEAR 1 Year Calendar Digi...

Page 325: ...BA 0x14 R W Time Scale Selection Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved 24H_12H Bits Description...

Page 326: ...ter Offset R W Description Reset Value DWR RTC_BA 0x18 R W Day of the Week Register 0x0000_0006 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4...

Page 327: ...HR 10 Hour Time Digit of Alarm Setting 0 2 19 16 1HR 1 Hour Time Digit of Alarm Setting 0 9 15 Reserved Reserved 14 12 10MIN 10 Min Time Digit of Alarm Setting 0 5 11 8 1MIN 1 Min Time Digit of Alarm...

Page 328: ...31 24 Reserved Reserved 23 20 10YEAR 10 Year Calendar Digit of Alarm Setting 0 9 19 16 1YEAR 1 Year Calendar Digit of Alarm Setting 0 9 15 13 Reserved Reserved 12 10MON 10 Month Calendar Digit of Ala...

Page 329: ...ister LIR Register Offset R W Description Reset Value LIR RTC_BA 0x24 R Leap Year Indicator Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8...

Page 330: ...bit is used to enable disable RTC Time Tick Interrupt and generate an interrupt signal if TIF RIIR 1 RTC Time Tick Interrupt Flag is set to 1 0 RTC Time Tick Interrupt Disabled 1 RTC Time Tick Interru...

Page 331: ...his bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TIER RIER 1 is set to 1 Chip will also be wake up if RTC Tick Interrupt is enabled and this bit is set to 1 wh...

Page 332: ...d 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TTR Bits Description 31 3 Reserved Reserved 2 0 TTR Time Tick Register These bits are used to select RTC time tick period for Periodic Time Ti...

Page 333: ...eserved Bits Description 31 8 Reserved Reserved 7 SPRRDY SPR Register Ready This bit indicates if the registers SPRCTL SPR0 SPR19 are ready to be accessed After user writing registers SPRCTL SPR0 SPR1...

Page 334: ...R W RTC Spare Register 7 0x0000_0000 SPR8 RTC_BA 0x60 R W RTC Spare Register 8 0x0000_0000 SPR9 RTC_BA 0x64 R W RTC Spare Register 9 0x0000_0000 SPR10 RTC_BA 0x68 R W RTC Spare Register 10 0x0000_000...

Page 335: ...029LEE NUC029SEE TECHNICAL REFERENCE MANUAL Bits Descriptions 31 0 SPARE Spare Register This field is used to store back up information defined by user Before storing back up information in to SPARE r...

Page 336: ...auto flow control flow control function CTS RTS and programmable RTS flow control trigger level UART0 and UART1 support Programmable receiver buffer trigger level Supports programmable baud rate gene...

Page 337: ...lock switching both the pre selected and newly selected clock sources must be turned on and stable 11 10 01 00 PLL FOUT 4 24 MHz 22 1184 MHz UART_S CLKSEL1 25 24 UART0_EN APBCLK 16 UART0_CLK 1 UART_N...

Page 338: ...atus Register This field is register set that including the FIFO control registers UA_FCR FIFO status registers UA_FSR and line control register UA_LCR for transmitter and receiver The time out contro...

Page 339: ...receiver need The baud rate equation is Baud Rate UART_CLK M BRD 2 where M and BRD are defined in Baud Rate Divider Register UA_BAUD The following tables list the UART baud rate equations in the vario...

Page 340: ...30400 A 4 A 4 B 15 A 6 B 11 A 94 115200 A 10 A 10 B 15 A 14 B 11 A 190 57600 A 22 A 22 B 15 A 30 B 11 A 382 38400 A 34 A 62 B 8 A 46 B 11 A 34 B 15 A 574 19200 A 70 A 126 B 8 A 94 B 11 A 70 B 15 A 115...

Page 341: ...E 0x3000_08FE 4800 0x0000_011E 0x2800_01FE 0x2B00_017E 0x2F00_011E 0x3000_11FE Table 6 13 4 UART Controller Baud Rate Register UA_BAUD Setting Table 6 13 5 2UART Controller Transmit Delay Time Value T...

Page 342: ..._INT Line status interrupt parity error frame error or break interrupt RLS_INT MODEM Wake up status interrupt MODEM_INT Receiver buffer time out interrupt TOUT_INT Buffer error interrupt BUF_ERR_INT L...

Page 343: ...NT MODEM_IEN MODEM_IF DCTSF Write 1 to DCTSF RX Time out Interrupt TOUT_INT RTO_IEN HW_TOUT_IF Read UA_RBR Buffer Error Interrupt BUF_ERR_INT BUF_ERR_IEN HW_BUF_ERR_IF TX_OVER_IF Write 1 to RFR HW_BUF...

Page 344: ...ata stream and adding a parity bit to the total bits to make the count an even number Forced Mask Parity 1 0 1 Parity bit always logic 1 Parity bit on the serial byte is set to 1 regardless of total n...

Page 345: ...V_CTS UA_MCR 8 can set CTS pin input active state The DCTSF UA_MSR 0 is set when any state change of CTS pin input has occurred and then TX data will be automatically transmitted from TX FIFO LEV_CTS...

Page 346: ...y software programming of RTS UA_MCR 1 control bit Setting LEV_RTS UA_MCR 9 can control the RTS pin output is inverse or non inverse from RTS UA_MCR 1 control bit User can read the RTS_ST UA_MCR 13 bi...

Page 347: ...on Return to Zero NRZ transmit bit stream output from UART The IrDA SIR physical layer specifies the use of Return to Zero Inverted RZI modulation scheme which represents logic 0 as an infra light pul...

Page 348: ...ports header detection and automatic resynchronization in LIN Slave mode 6 13 5 8 1 Structure of LIN Frame According to the LIN protocol all information transmitted is packed as frames a frame consist...

Page 349: ...ected mode can be break field or break field and sync field or break field sync field and frame ID field by setting LIN_HEAD_SEL UA_LIN_CTL 23 22 If the selected header is break field software must ha...

Page 350: ...1 bit time Setting LIN_BS_LEN UA_LIN_CTL 21 20 and DLY UA_TOR 7 0 can change break sync delimiter length and inter byte spaces Note3 If the header includes the break field sync field and frame ID fiel...

Page 351: ...DET_F 1 2 3 4 5 6 7 8 9 10 11 Case 2 Break signal is long enough to break detect and LIN_BKDET_F has been set LIN Bus IDLE Capture Strobe 0 Delimiter LIN_BKDET_F 1 2 3 4 5 6 7 8 9 10 11 Case 1 Break s...

Page 352: ...er detection function by setting the LINS_HDET_EN UA_LIN_CTL 10 to detect complete frame header receive break field sync field and frame ID field When a LIN header is received the LINS_HDET_F UA_LIN_S...

Page 353: ...ntroller will enable the receiver exit from Mute mode and subsequent data sync data frame ID data response data are received in RX FIFO If LIN_HEAD_SEL UA_LIN_CTL 23 22 is set to break field and sync...

Page 354: ...6 13 14 LIN Sync Field Measurement When operating in Automatic Resynchronization mode software must select the desired baud rate by setting the UA_BAUD register and hardware will store it at internal...

Page 355: ...lue is UA_BAUD n BAUD_LIN value is UA_BAUD m Both of TEMP_REG and BAUD_LIN are internal register Figure 6 13 15 UA_BAUD Update Sequence in Automatic Resynchronization Mode when LINS_DUM_EN UA_LIN_CTL...

Page 356: ...and 15 62 the header error flag LINS_HERR_F UA_LIN_SR 1 may either set or not Note The deviation check is based on the current baud rate clock Therefore in order to guarantee correct deviation checkin...

Page 357: ...R 8 then enable RS485_NMM UA_ALT_CSR 8 and the receiver will ignore any data until an address byte is detected bit 9 1 and the address byte data will be stored in the RX FIFO If software wants to rece...

Page 358: ...level is controlled by programing the RTS UA_MCR 1 control bit Setting LEV_RTS UA_MCR 9 can control the RTS pin output is inverse or non inverse from RTS UA_MCR 1 control bit User can read the RTS_ST...

Page 359: ...ne auto direction control by programming RS485_AUD UA_ALT_CSR 10 Start bit D0 TX pin output RTS_ST UA_MCR 13 Driver Enable RX TX RTS Differential Bus RS 485 Transceiver UART RS 485 Controller D1 D2 D3...

Page 360: ...08 R W UART FIFO Control Register 0x0000_0101 UA_LCR x 0 1 2 UARTx_BA 0x0C R W UART Line Control Register 0x0000_0000 UA_MCR x 0 1 UARTx_BA 0x10 R W UART Modem Control Register 0x0000_0200 UA_MSR x 0...

Page 361: ...crocontroller Aug 2018 Page 361 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL UA_LIN_CTL x 0 1 2 UARTx_BA 0x34 R W UART LIN Control Register 0x000C_0000 UA_LIN_SR x 0 1 2 UART...

Page 362: ...UA_RBR Register Offset R W Description Reset Value UA_RBR x 0 1 2 UARTx_BA 0x00 R UART Receive Buffer Register Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 1...

Page 363: ...x 0 1 2 UARTx_BA 0x00 W UART Transmit Holding Register Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 THR Bits Description 3...

Page 364: ...ble RX DMA service 0 RX DMA Disabled 1 RX DMA Enabled 14 DMA_TX_EN TX DMA Enable Bit Not Available In UART2 Channel This bit can enable or disable TX DMA service 0 TX DMA Disabled 1 TX DMA Enabled 13...

Page 365: ...s in Power down mode an external CTS change will wake up chip from Power down mode 5 BUF_ERR_IEN Buffer Error Interrupt Enable Bit 0 BUF_ERR_INT Masked off 1 BUF_ERR_INT Enabled 4 TOUT_IEN RX Time Out...

Page 366: ...30 14 bytes High Speed Normal Speed 0101 RTS Trigger Level is 46 14 bytes High Speed Normal Speed 0110 RTS Trigger Level is 62 14 bytes High Speed Normal Speed Other Reserved Note This field is used f...

Page 367: ...R TX Field Software Reset When TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared 0 No effect 1 Reset the TX internal state machine and pointers Note This bit will...

Page 368: ...y Disabled 1 If PBE UA_LCR 3 and EBE UA_LCR 4 are logic 1 the parity bit is transmitted and checked as logic 0 If PBE UA_LCR 3 is 1 and EBE UA_LCR 4 is 0 then the parity bit is transmitted and checked...

Page 369: ...n output is high level voltage logic state 12 10 Reserved Reserved 9 LEV_RTS RTS Pin Active Level Not Available In UART2 Channel This bit defines the active level state of RTS pin output 0 RTS pin out...

Page 370: ...nput is high level active 1 CTS pin input is low level active Note Refer to Figure 6 13 5 for more information 7 5 Reserved Reserved 4 CTS_ST CTS Pin Status Read Only Not Available In UART2 Channel Th...

Page 371: ...been transmitted 0 TX FIFO is not empty 1 TX FIFO is empty Note This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed 27 25 Reserved Reserved 24 T...

Page 372: ...r Read Only This field indicates the RX FIFO Buffer Pointer When UART receives one byte from external device then RX_POINTER increases one When one byte of RX FIFO is read by CPU then RX_POINTER decre...

Page 373: ...at is an address bit bit 9 1 Note1 This field is used for RS 485 function mode and RS485_ADD_EN UA_ALT_CSR 15 is set to 1 to enable Address detection mode Note2 This bit is read only but can be cleare...

Page 374: ...F_ERR_IF UA_ISR 5 are both set to 1 0 No buffer error interrupt is generated in DMA mode 1 Buffer error interrupt is generated in DMA mode 28 HW_TOUT_INT In DMA Mode Time Out Interrupt Indicator Read...

Page 375: ...0 when the bit DCTSF US_MSR 0 is cleared by writing 1 on DCTSF US_MSR 0 18 HW_RLS_IF In DMA Mode Receive Line Status Flag Read Only This bit is set when the RX receive data have parity error frame err...

Page 376: ...IN_ IEN UA_IER 8 is enabled the LIN interrupt will be generated 0 None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F LINS_IDPERR_F and LINS_HERR_F is generated 1 At least one of LINS_HDET_F LIN_BKDET_F BIT_ERR...

Page 377: ...bit of UA_FSR RS485_ADD_DETF is also set Note2 This bit is read only and reset to 0 when all bits of BIF UA_FSR 6 FEF UA_FSR 5 and PEF UA_FSR 4 are cleared Note3 In RS 485 function mode this bit is r...

Page 378: ...tart bit 7 0 TOIC Time Out Interrupt Comparator The time out counter resets and starts counting the counting clock baud rate whenever the RX FIFO receives a new data word Once the content of time out...

Page 379: ...d Reserved 29 DIV_X_EN Divider X Enable Bit The BRD Baud Rate Divider and the baud rate equation is Baud Rate Clock M BRD 2 The default value of M is 16 0 Divider X Disabled the equation of M 16 1 Div...

Page 380: ...0 Reserved INV_RX INV_TX Reserved TX_SELECT Reserved Bits Description 31 7 Reserved Reserved 6 INV_RX IrDA Inverse Receive Input Signal Control 0 None inverse receiving input signal 1 Inverse receivi...

Page 381: ...N RS 485 Address Detection Enable Bit This bit is used to enable RS 485 Address Detection mode 0 Address detection mode Disabled 1 Address detection mode Enabled Note This bit is used for RS 485 any o...

Page 382: ...led Note When TX break field transfer operation finished this bit will be cleared automatically 6 LIN_RX_EN LIN RX Enable Bit 0 LIN RX mode Disabled 1 LIN RX mode Enabled 5 4 Reserved Reserved 3 0 LIN...

Page 383: ...Description Reset Value UA_FUN_SEL x 0 1 2 UARTx_BA 0x30 R W UART Function Select Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved...

Page 384: ...If the parity generated by hardware user fill ID0 ID5 LIN_PID 29 24 hardware will calculate P0 LIN_PID 30 and P1 LIN_PID 31 otherwise user must filled frame ID and parity in this field Note1 User can...

Page 385: ...led LIN_RX_DIS UA_LIN_CTL 11 1 all received byte data will be ignore 0 LIN receiver Enabled 1 LIN receiver Disabled Note This bit is only valid when operating in LIN function mode FUN_SEL UA_FUN_SEL 1...

Page 386: ...synchronization mode for Non Automatic Resynchronization mode this bit should be kept cleared Note3 The control and interactions of this field are explained in 6 13 5 8 4 Slave mode with automatic res...

Page 387: ...o it Note2 This bit is only valid when enable bit error detection function BIT_ERR_EN UA_LIN_CTL 12 1 8 LIN_BKDET_F LIN Break Detection Flag Read Only This bit is set by hardware when a break is detec...

Page 388: ...ynchronization mode sync field deviation error with Automatic Resynchronization mode sync field measure time out with Automatic Resynchronization mode and LIN header reception time out 0 LIN header er...

Page 389: ...L to transfer information between devices connected to the bus The main features of the I 2 C bus include Supports up to two I 2 C serial interface controller Master Slave mode Bidirectional data tran...

Page 390: ...setting I2C1_EN APBCLK 9 Reset I 2 C1 controller by setting I2C1_RST IPRSTC2 9 6 14 4 Block Diagram The basic configurations of I2 C are as follows Control Register APB Interface Bus Clock Control Wa...

Page 391: ...this port ENS1 I2CON 6 should be set to 1 The I 2 C hardware interfaces to the I 2 C bus via two pins I2Cn_SDA and I2Cn_SCL When I O pins are used as I 2 C ports user must set the pins function to I 2...

Page 392: ...P signal usually referred to as the P bit is defined as a LOW to HIGH transition on the I2Cn_SDA line while I2Cn_SCL is HIGH The following figure shows the waveform of START Repeat START and STOP STOP...

Page 393: ...he following figure shows a master transmits data to slave A master addresses a slave with a 7 bit address and 1 bit write index to denote that the master wants to transmit data to the slave The maste...

Page 394: ...port switches to Slave mode immediately and can detect its own slave address in the same serial transfer To control the I 2 C bus transfer in each mode user needs to set I2CON I2CDAT registers accord...

Page 395: ...NAK Master to Slave Slave to Master I2CDAT Data ACK NAK Sr P P S STATUS 0x08 STA STO SI AA 1 0 1 X ACK STATUS 0x18 NAK STATUS 0x20 I2CDAT SLA W STA STO SI AA 0 0 1 X ACK STATUS 0x28 NAK STATUS 0x30 I...

Page 396: ...O SI AA 0 0 1 X I2 C bus will be release Not addressed SLV mode will be enterd STA STO SI AA 1 0 1 X A START will be transmitted when the bus becomes free Enter not addressed SLV mode Send a START whe...

Page 397: ...a STA STO SI AA 0 0 1 1 I2CDAT Data I2CDAT Data STA STO SI AA 0 0 1 0 STATUS 0xB8 Switch to not addressed mode Own SLA will be recognized ACK I2CDAT Data I2CDAT Data STA STO SI AA 0 0 1 0 NAK STATUS 0...

Page 398: ...to I 2 C bus then it will follow status of GC mode S I2CDAT SLA W 0x00 ACK STA STO SI AA 0 0 1 1 GC 1 STATUS 0x70 I2CDAT Data ACK NAK STA STO SI AA 0 0 1 1 I2CDAT Data STA STO SI AA 0 0 1 0 STATUS 0x...

Page 399: ...ration is performed on the I2Cn_SDA signal while the I2Cn_SCL signal is high Each master checks if the I2Cn_SDA signal on the bus corresponds to the generated I2Cn_SDA signal If the I2Cn_SDA signal on...

Page 400: ...th four address mask registers I2CADMn n 0 3 When the bit in the address mask register is set to 1 it means the received corresponding address bit is Don t care If the bit is set to 0 it means the rec...

Page 401: ...ntered a status interrupt is requested SI I2CON 3 1 A valid status code is present in I2CSTATUS 7 0 one cycle after SI set by hardware and is still present one cycle after SI reset by software In addi...

Page 402: ...rflows TIF I2CTOC 0 1 and generates I 2 C interrupt to CPU or stops counting by clearing ENTI I2CTOC 2 to 0 When time out counter is enabled writing 1 to the SI I2CON 3 flag will reset counter and re...

Page 403: ...ON 6 1 to enable I 2 C0 controller 5 Write a divided value by setting I2CLK register for I 2 C clock rate 6 Set SETENA NVIC_ISER 31 0 0x00040000 in the NVIC_ISER register to set I 2 C0 IRQ 7 Set EI I2...

Page 404: ...SLA R STA STO SI AA 0 0 1 X STATUS 0x40 NAK STATUS 0x20 I2CDAT ROM Address Low Byte ACK STATUS 0x28 I2CDAT ROM Address Low Byte STA STO SI AA 0 0 1 X P STATUS 0xF8 STA STO SI AA 0 1 1 X NAK STATUS 0x3...

Page 405: ...BA 0x10 R W I2 C Clock Divided Register 0x0000_0000 I2CTOC n 0 1 I2Cn_BA 0x14 R W I2 C Time out Counter Register 0x0000_0000 I2CADDR1 n 0 1 I2Cn_BA 0x18 R W I2 C Slave Address Register1 0x0000_0000 I2...

Page 406: ...STA to logic 1 to enter Master mode the I2 C hardware sends a START or repeat START condition to bus when the bus is free 4 STO I2 C STOP Control In Master mode setting STO to transmit a STOP conditio...

Page 407: ...Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL acknowledging the data sent by transmitter When AA 0 prior to address or data received a Not acknowledged high level to I2Cn_SDA will b...

Page 408: ...2CDAT Register Offset R W Description Reset Value I2CDAT n 0 1 I2Cn_BA 0x08 R W I2 C Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 R...

Page 409: ...C Status Register There are 26 possible status codes When I2CSTATUS contains 0xF8 no serial interrupt is requested All other I2CSTATUS values correspond to defined I2 C states When each of these stat...

Page 410: ...R W Description Reset Value I2CLK n 0 1 I2Cn_BA 0x10 R W I2 C Clock Divided Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5...

Page 411: ...0 Reserved ENTI DIV4 TIF Bits Description 31 3 Reserved Reserved 2 ENTI Time Out Counter Enable Bit 0 Disabled 1 Enabled When Enabled the 14 bit time out counter will start counting when SI I2CON 3 is...

Page 412: ...e Address Register2 0x0000_0000 I2CADDR3 n 0 1 I2Cn_BA 0x20 R W I2 C Slave Address Register3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserve...

Page 413: ...x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 I2CADM Reserved Bits Description 31 8 Reserved Reserved 7 1 I2CADM I2 C Addr...

Page 414: ...PCON Register Offset R W Description Reset Value I2CWKUPCON n 0 1 I2Cn_BA 0x3C R W I2 C Wake up Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 415: ...Reset Value I2CWKUPSTS n 0 1 I2Cn_BA 0x40 R W I2 C Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0...

Page 416: ...pheral device Each set of SPI controller can be configured as a master or a slave device The SPI controller supports the variable bus clock function for special applications This controller also suppo...

Page 417: ...c configurations of SPI0 are as follows SPI0 pin functions are configured in ALT_MFP GPB_MFP and GPC_MFP registers Select the source of SPI0 peripheral clock on SPI0_S CLKSEL1 4 Enable SPI0 peripheral...

Page 418: ...ual to the SPI peripheral clock rate In general the SPI bus clock is denoted as SPI clock In Slave mode the SPI bus clock is provided by an off chip master device The SPI peripheral clock rate of slav...

Page 419: ...her on negative edge or on positive edge of SPI bus clock Receive Edge RX_NEG SPI_CNTRL 1 defines the data received either on negative edge or on positive edge of SPI clock Note The settings of TX_NEG...

Page 420: ...rupt flag will be set User can read the status of LTRIG_FLAG bit to check if the data has been completely transferred 6 15 5 2Automatic Slave Selection In Master mode if AUTOSS SPI_SSR 3 is set to 1 t...

Page 421: ...will be rearranged in the order as Byte0 Byte1 Byte2 Byte3 in 32 bit Transfer mode TX_BIT_LEN 0 The sequence of transmitted received data will be Byte0 Byte1 Byte2 and then Byte3 If the TX_BIT_LEN is...

Page 422: ...be configured as a GPIO When the NOSLVSEL bit is set to 1 the SPI slave will be ready to transmit receive data after the GO_BUSY bit is set to 1 As the number of received bits meets the requirement wh...

Page 423: ...ts FIFO mode when the FIFO bit in SPI_CNTRL 21 is set as 1 The SPI controllers equip with eight 32 bit wide transmit and receive FIFO buffers The transmit FIFO buffer is an 8 layer depth 32 bit wide f...

Page 424: ...e buffer 2 Transmit buffer n Transmit buffer 2 Receive buffer 1 Transmit buffer 1 SPIn_MOSI0 Pin in Master Mode or SPIn_MISO0 Pin in Slave Mode SPIn_MISO0 Pin in Master Mode or SPIn_MOSI0 Pin in Slave...

Page 425: ...he slave senses the SPI clock signal The SPI controller will issue an interrupt if the SSTA_INTEN is set to 1 If the count of the received bits is less than the setting of TX_BIT_LEN and there is no m...

Page 426: ...RX0 4 RX0 2 LSB RX0 0 MSB RX0 7 RX0 3 MSB TX0 7 SPIn_SS0 CLKP 0 CLKP 1 TX0 5 RX0 5 TX0 1 RX0 1 SS_LVL 0 SS_LVL 1 Master Mode CNTRL SLVAE 0 CNTRL LSB 0 CNTRL TX_BIT_LEN 0x08 1 CNTRL CLKP 0 CNTRL TX_NE...

Page 427: ...LSB 0 CNTRL TX_BIT_LEN 0x08 1 CNTRL CLKP 0 CNTRL TX_NEG 1 CNTRL RX_NEG 0 or 2 CNTRL CLKP 1 CNTRL TX_NEG 0 CNTRL RX_NEG 1 Figure 6 15 13 SPI Timing in Slave Mode SPIn_CLK SPIn_MOSI0 SPIn_MISO0 TX0 1 TX...

Page 428: ...output active at the I O pin by setting the Slave Select Register bit SSR 0 SPI_SSR 0 to active the off chip slave device 3 Write the related settings into the SPI_CNTRL register to control the SPI ma...

Page 429: ..._CNTRL register to control this SPI slave actions 1 Set the SPI controller as slave device in SLAVE bit SPI_CNTRL 18 1 2 Select the SPI clock idle state at high in CLKP bit SPI_CNTRL 11 1 3 Select dat...

Page 430: ...1 SPIn_BA 0x04 R W Clock Divider Register 0x0000_0000 SPI_SSR n 0 1 SPIn_BA 0x08 R W Slave Select Register 0x0000_0000 SPI_RX0 n 0 1 SPIn_BA 0x10 R Data Receive Register 0 0x0000_0000 SPI_TX0 n 0 1 S...

Page 431: ...FIFO buffer is not full 1 Transmit FIFO buffer is full 26 TX_EMPTY Transmit FIFO Buffer Empty Indicator Read Only It is a mutual mirror bit of SPI_STATUS 26 0 Transmit FIFO buffer is not empty 1 Tran...

Page 432: ...t be kept at active state during the byte suspend interval Note3 The Byte Reorder function is not supported when the variable bus clock function or Dual I O mode is enabled 18 SLAVE Slave Mode EnableB...

Page 433: ...is changed on the falling edge of SPI bus clock 1 RX_NEG Receive On Negative Edge 0 Received data input signal is latched on the rising edge of SPI bus clock 1 Received data input signal is latched o...

Page 434: ...ency divider for generating the second clock of the variable clock function The frequency is obtained according to the following equation 2 1 2 _ 2 DIVIDER f f eclk spi clock If the VARCLK_EN bit is c...

Page 435: ...mode this bit has no meaning 4 SS_LTRIG Slave Select Level Trigger Enable Bit Slave Only 0 Slave select signal is edge trigger This is the default value The SS_LVL bit decides the signal is active aft...

Page 436: ...f the AUTOSS bit is set writing 0 to this field will keep the SPIn_SPISS0 line at inactive state writing 1 to this field will select SPIn_SPISS0 line to be automatically driven to active state for the...

Page 437: ...24 RX 23 22 21 20 19 18 17 16 RX 15 14 13 12 11 10 9 8 RX 7 6 5 4 3 2 1 0 RX Bits Description 31 0 RX Data Receive Register The data receive register holds the datum received from SPI data input pin I...

Page 438: ...o be transmitted in the next transfer The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register For example if TX_BIT_LEN is set to 0x08 the bits TX 7 0 wi...

Page 439: ...e SPI_VARCLK SPIn_BA 0x34 R W Variable Clock Pattern Register 0x007F_FF87 31 30 29 28 27 26 25 24 VARCLK 23 22 21 20 19 18 17 16 VARCLK 15 14 13 12 11 10 9 8 VARCLK 7 6 5 4 3 2 1 0 VARCLK Bits Descrip...

Page 440: ...is recommended if the software uses more than one PDMA channel to transfer data In Slave mode and when FIFO mode is disabled if the software only uses one PDMA channel for SPI receive PDMA function a...

Page 441: ...details 30 17 Reserved Reserved 16 SS_INT_OPT Slave Select Inactive Interrupt Option This setting is only available if the SPI controller is configured as level trigger slave device 0 As the slave se...

Page 442: ...ire Mode Abort Control In normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN If the received bits are less than the requirement and...

Page 443: ...han or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0 27 Reserved Reserved 26 24 RX_THRESHOLD Receive FIFO Threshold If the valid data...

Page 444: ...r 0 No effect 1 Clear transmit FIFO buffer The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1 This bit will be cleared to 0 by hardware after it is set to 1 by software 0 RX_...

Page 445: ...ual mirror bit of SPI_CNTRL 27 0 Transmit FIFO buffer is not full 1 Transmit FIFO buffer is full 26 TX_EMPTY Transmit FIFO Buffer Empty Indicator Read Only It is a mutual mirror bit of SPI_CNTRL 26 0...

Page 446: ...lave 3 wire mode It will be cleared as a transaction is done or by writing 1 to this bit 10 5 Reserved Reserved 4 TX_INTSTS Transmit FIFO Threshold Interrupt Status Read Only 0 The valid data count wi...

Page 447: ...ge the data sequential synchronization endpoint states current start address transaction status and data buffer status for each endpoint There are four different interrupt events in this controller Th...

Page 448: ...cription 6 16 5 1SIE Serial Interface Engine The SIE is the front end of the device controller and handles most of the USB packet protocol The SIE typically comprehends signaling up to the transaction...

Page 449: ...SB cable is plugged in If user polls the flag to check USB state software de bouncing must be added if needed 6 16 5 5Interrupt This USB provides 1 interrupt vector with 4 interrupt events WAKE UP FLD...

Page 450: ...automatically to save power while this chip enters Power down mode User can write 0 into USB_ATTR 4 to disable PHY under special circumstances like suspend to save power 6 16 5 7Buffer Control There i...

Page 451: ...Buffer 8 bytes EP0 SRAM Buffer 64 bytes EP1 SRAM Buffer 64 bytes EP2 SRAM Buffer EP3 SRAM Buffer USB SRAM Start Address EP0 SA USBD_BA 0x0108h MXPLD0 0x40 USB SRAM USBD_BA 0x0100h EP1 SA USBD_BA 0x01...

Page 452: ...fied data the signal In_Rdy will be de asserted automatically by hardware USB_IRQ In_Rdy Data In Setup PID Data Setup ACK PID IN PID NAK PID IN PID Data 0 1 ACK PID USB Bus Packets Setup Received Setu...

Page 453: ..._MXPLD0 USBD_BA 0x504 R W Endpoint 0 Maximal Payload Register 0x0000_0000 USB_CFG0 USBD_BA 0x508 R W Endpoint 0 Configuration Register 0x0000_0000 USB_CFGP0 USBD_BA 0x50C R W Endpoint 0 Set Stall and...

Page 454: ...5 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USB_BUFSEG6 USBD_BA 0x560 R W Endpoint 6 Buffer Segmentation Register 0x0000_0000 USB_MXPLD6 USBD_BA 0x564 R W Endpoint 6 Maximal Payloa...

Page 455: ...N token IN NAK status will not be updated to USBD_EPSTS register so that the USB interrupt event will not be asserted 1 IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event...

Page 456: ...ind of USB event was occurred cleared by write 1 to USB_INTSTS 23 or USB_INTSTS 1 22 EPEVT6 Endpoint 6 s USB Event Status 0 No event occurred on endpoint 6 1 USB event occurred on Endpoint 6 check USB...

Page 457: ...ved 4 4 SOSOF_STS Start of Frame Interrupt Status 0 SOF event does not occur 1 SOF event occurred cleared by write 1 to USBD_INTSTS 4 3 WAKEUP_STS Wake Up Interrupt Status 0 No Wake up event occurred...

Page 458: ...ADDR A 7 bit value is used as the address of a device on the USB BUS Register Offset R W Description Reset Value USB_FADDR USBD_BA 0x008 R W USB Device Function Address Register 0x0000_0000 31 30 29 2...

Page 459: ...tus These bits are used to indicate the current status of this endpoint 000 In ACK 001 In NAK 010 Out Packet Data0 ACK 110 Out Packet Data1 ACK 011 Setup ACK 111 Isochronous transfer end 28 26 EPSTS6...

Page 460: ...point 000 In ACK 001 In NAK 010 Out Packet Data0 ACK 110 Out Packet Data1 ACK 011 Setup ACK 111 Isochronous transfer end 13 11 EPSTS1 Endpoint 1 Bus Status These bits are used to indicate the current...

Page 461: ...er from CPU to USB SRAM can be Word only 1 Byte mode The size of the transfer from CPU to USB SRAM can be Byte only 9 PWRDN Power Down PHY Transceiver Low Active 0 Power down related circuit of PHY tr...

Page 462: ...SUME Resume Status 0 No bus resume 1 Resume from suspend Note This bit is read only 1 SUSPEND Suspend Status 0 Bus no suspend 1 Bus idle more than 3ms either cable is plugged off or host is sleeping N...

Page 463: ...ster Offset R W Description Reset Value USB_FLDET USBD_BA 0x014 R USB Floating Detection Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Re...

Page 464: ...egister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved STBUFSEG 8 7 6 5 4 3 2 1 0 STBUFSEG 7 3 Reserved Bits Description 31 9 Reserved Res...

Page 465: ...ster USBD_FN Register Offset R W Description Reset Value USBD_FN USBD_BA 0x08C R USB Frame Number Register 0x0000_0XXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 466: ...ntation Register 0x0000_0000 USB_BUFSEG5 USBD_BA 0x55 0 R W Endpoint 5 Buffer Segmentation Register 0x0000_0000 USB_BUFSEG6 USBD_BA 0x56 0 R W Endpoint 6 Buffer Segmentation Register 0x0000_0000 USB_B...

Page 467: ...0 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved MXPLD 7 6 5 4 3 2 1 0 MXPLD Bits Description 31 9 Reserved Reserved 8 0 MXPLD Maximal Payload Define the da...

Page 468: ...gister 0x0000_0000 USB_CFG6 USBD_BA 0x568 R W Endpoint 6 Configuration Register 0x0000_0000 USB_CFG7 USBD_BA 0x578 R W Endpoint 7 Configuration Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23...

Page 469: ...CRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 4 ISOCH Isochronous Endpoint This bit is used to set the endpoint as Isochronous endpoint no handshake 0 No Isochronous endpoint 1 Isochronous endpoi...

Page 470: ...ol Register 0x0000_0000 USB_CFGP6 USBD_BA 0x56 C R W Endpoint 6 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USB_CFGP7 USBD_BA 0x57 C R W Endpoint 7 Set Stall and Clear In Out Ready C...

Page 471: ...et Value USB_DRVSE0 USBD_BA 0x090 R W USB Drive SE0 Control Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserv...

Page 472: ...e chip working at 5V Three operating modes Single mode A D conversion is performed one time on a specified channel Single cycle scan mode A D conversion is performed one cycle on all specified channel...

Page 473: ...re Register ADCMPR ADC0 ADC1 ADC11 16 to 1 Analog MUX Sample and Hold Comparator PDMA request RSLT 11 0 ADC_INT STADC Analog Macro ADC clock and ADC start signal VREF ADC channel select APB Bus VALID...

Page 474: ...4 24 MHz 22 1184 MHz ADC_S CLKSEL1 3 2 ADC_EN APBCLK 28 ADC_CLK 1 ADC_N 1 ADC_N CLKDIV 23 16 HCLK Note Before clock switching both the pre selected and newly selected clock sources must be turned on...

Page 475: ...ut A D conversion starts on the channel with the smallest number 2 When A D conversion for each enabled channel is completed the result is sequentially transferred to the A D data register correspondi...

Page 476: ...ADST bit ADCR 11 is set to 1 by software A D conversion starts on the channel with the smallest number 2 When A D conversion for each enabled channel is completed the result of each enabled channel is...

Page 477: ...hannels Timing Diagram 6 17 5 5Internal Reference Voltage The band gap voltage reference VBG is an internal fixed reference voltage regardless of power supply variations The VBG output is internally c...

Page 478: ...rigger Input Sampling and A D Conversion Time In single cycle scan mode A D conversion can be triggered by external pin request When the TRGEN ADCR 8 is set to high to enable ADC external trigger func...

Page 479: ...es not match during the comparing the compare match counter will clear to 0 When counter value reach the setting of CMPMATCNT ADCMPR0 1 11 8 1 then CMPF0 1 bit ADSR 1 2 will be set to 1 if CMPIE bit A...

Page 480: ...emory space without CPU s intervention The source address of PDMA operation is fixed at ADPDMA no matter what channels was selected When PDMA is transferring the conversion result ADC will continue co...

Page 481: ...er 4 0x0000_0000 ADDR5 ADC_BA 0x14 R ADC Data Register 5 0x0000_0000 ADDR6 ADC_BA 0x18 R ADC Data Register 6 0x0000_0000 ADDR7 ADC_BA 0x1C R ADC Data Register 7 0x0000_0000 ADCR ADC_BA 0x20 R W ADC Co...

Page 482: ...000 ADDR6 ADC_BA 0x18 R ADC Data Register 6 0x0000_0000 ADDR7 ADC_BA 0x1C R ADC Data Register 7 0x0000_0000 ADDR8 ADC_BA 0x50 R ADC Data Register 8 0x0000_0000 ADDR9 ADC_BA 0x54 R ADC Data Register 9...

Page 483: ...n Result This field contains conversion result of ADC When DMOF bit ADCR 31 set to 0 12 bit ADC conversion result with unsigned format will be filled in RSLT ADDRx 11 0 x 0 11 and zero will be filled...

Page 484: ...0_0001 1000_0000_0000 0111_1111_1111 0 1 LSB Vref 4096 1111_1000_0000_0000 1111_1000_0000_0001 1111_1000_0000_0010 0000_0111_1111_1111 0000_0111_1111_1110 0000_0111_1111_1101 Vref 1 LSB Vref 1 LSB Dif...

Page 485: ...A D Differential Input Mode Output Format 0 A D Conversion result will be filled in RSLT at ADDRx registers with unsigned format 1 A D Conversion result will be filled in RSLT at ADDRx registers with...

Page 486: ...e converted data is loaded into ADDR 0 11 software can enable this bit to generate a PDMA data transfer request When PTEN 1 software must set ADIE 0 ADCR 1 to disable interrupt 8 TRGEN Hardware Trigge...

Page 487: ...When changing the operation mode software should disable ADST bit ADCR 11 firstly 1 ADIE A D Interrupt Enable Bit 0 A D interrupt function Disabled 1 A D interrupt function Enabled A D conversion end...

Page 488: ...ed 13 10 CHEN1 Analog Input Channel Enable Bit 1 Set CHEN 14 10 to enable the corresponding analog input channel 11 8 If DIFFEN bit ADCR 10 is set to 1 only the even number channels need to be enabled...

Page 489: ...of specified channel When DMOF bit ADCR 31 is set to 0 ADC comparator compares CMPD with conversion result with unsigned format CMPD should be filled in unsigned format When DMOF bit ADCR 31 is set t...

Page 490: ...mpared 2 CMPCOND Compare Condition 0 Set the compare condition as that when a 12 bit A D conversion result is less than the 12 bit CMPD ADCMPR0 1 27 16 the internal match counter will increase one 1 S...

Page 491: ...It is read only 23 16 OVERRUN0 Overrun Flag It is a mirror to OVERRUN bit ADDR0 7 16 It is read only 15 8 VALID0 Data Valid Flag It is a mirror of VALID bit ADDR0 7 17 It is read only 7 4 CHANNEL Cur...

Page 492: ...0 then this bit is set to 1 And it is cleared by writing 1 to self 0 Conversion result in ADDR does not meet ADCMPR0 setting 1 Conversion result in ADDR meets ADCMPR0 setting 0 ADF A D Conversion End...

Page 493: ...C_BA 0x40 R ADC PDMA Current Transfer Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved AD_PDMA 15 14 13 12 11 10 9 8 AD_PDMA 7 6 5 4 3 2 1 0 AD_PDMA Bits Des...

Page 494: ...ontroller Aug 2018 Page 494 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 7 ELECTRICAL CHARACTERISTICS For information on NuMicro NUC029LEE NUC029SEE electrical characteristic...

Page 495: ...UC029LEE NUC029SEE 32 bit Arm Cortex M0 Microcontroller Aug 2018 Page 495 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 8 PACKAGE DIMENSIONS 8 1 64 pin LQFP 7x7x1 4 mm footpri...

Page 496: ...NuMicro NUC029LEE NUC029SEE 32 bit Arm Cortex M0 Microcontroller Aug 2018 Page 496 of 497 Rev 1 00 NUMICRO NUC029LEE NUC029SEE TECHNICAL REFERENCE MANUAL 8 2 48 pin LQFP 7x7x1 4 mm footprint 2 0 mm...

Page 497: ...damage Such applications are deemed Insecure Usage Insecure usage includes but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instrumen...

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