NuMicro® NUC029LEE/NUC029SEE
32-bit Arm
®
Cortex
®
-M0 Microcontroller
Aug, 2018
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6.10.3 Block Diagram
The Watchdog Timer clock control and block diagram are shown as follows.
Note:
Before clock switching, both the pre-selected and newly selected
clock sources must be turned on and stable.
10
01
HCLK/2048
10 kHz LIRC
WDT_S (CLKSEL1[1:0])
WDT_EN (APBCLK[0])
WDT_CLK
11
32.768 kHz LXT
Legend:
LXT
= Low-Speed External clock signal
LIRC = Low-Speed Internal clock signal
Figure 6.10-1 Watchdog Timer Clock Control
Internal 18-bit WDT Up Counter
0
…
...
15
..
4
16
17
000
001
110
111
:
:
WDT_CLK
Time-out
Interval
Period
Select
Reset
Delay
Select
Watchdog
Interrupt
WTRE
(WTCR[1])
Watchdog
Reset
[1]
WTR (WTCR[0])
Reset WDT Counter
Note1:
WDT resets CPU and lasts 63 WDT_CLK.
Note2:
If user intends to use WDT to wake-up Idle/Power-down mode,
it is recommended that CPU clock source is set as the same as
WDT clock source before CPU enters in Power-down mode.
WTIE
(WTCR[6])
WTE
(WTCR[7])
WTIF
(WTCR[3])
WTRF
(WTCR[2])
WTIS
(WTCR[10:8])
Wake-up system from
Idle/Power-down mode
WTWKE
(WTCR[4])
WTWKF
(WTCR[5])
WTRDSEL
(WTCRALT[1:0])
Figure 6.10-2 Watchdog Timer Block Diagram