MS51
Dec. 17, 2019
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down mode suggest use WKT function see
Chapter 6.7 Self Wake-Up Timer (WKT).
6.6.1
Time-Out Reset Timer
When the CONFIG bits WDTEN[3:0] (CONFIG4[7:4]) is not FH, the WDT is initialized as a time-out
reset timer. If WDTEN[3:0] is not 5H, the WDT is allowed to continue running after the system enters
Idle or Power-down mode. Note that when WDT is initialized as a time-out reset timer, WDTR and
WIDPD has no function.
F
LIRC
WDCLR
WDPS[2:0]
WDT counter
(6-bit)
clear
overflow
WDT Reset
512-clock
Delay
10 kHz
Internal
Oscillator
WDTRF
WDTF
WDT Interrupt
clear
Pre-scalar
(1/1~1/256)
Figure 6.6-1 WDT as A Time-Out Reset Timer
After the device is powered and it starts to execute software code, the WDT starts counting
simultaneously. The time-out interval is selected by the three bits WDPS[2:0] (WDCON[2:0]). When
the selected time-out occurs, the WDT will set the interrupt flag WDTF (WDCON.5). If the WDT
interrupt enable bit EWDT (EIE0.4) and global interrupt enable EA are both set, the WDT interrupt
routine will be executed. Meanwhile, an additional 512 clocks of the low-speed internal oscillator
delays to expect a counter clearing by setting WDCLR to avoid the system reset by WDT if the device
operates normally. If no counter reset by writing 1 to WDCLR during this 512-clock period, a WDT
reset will happen. Setting WDCLR bit is used to clear the counter of the WDT. This bit is self-cleared
for user monitoring it. Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will
be set. This bit keeps unchanged after any reset other than a power-on reset. User may clear WDTRF
via software. Note that all bits in WDCON require timed access writing.
The main application of the WDT with time-out reset enabling is for the system monitor. This is
important in real-time control applications. In case of some power glitches or electro-magnetic
interference, CPU may begin to execute erroneous codes and operate in an unpredictable state. If this
is left unchecked the entire system may crash. Using the WDT during software development requires
user to select proper “Feeding Dog” time by clearing the WDT counter. By inserting the instruction of
setting WDCLR, it allows the code to run without any WDT reset. However If any erroneous code
executes by any interference, the instructions to clear the WDT counter will not be executed at the
required instants. Thus the WDT reset will occur to reset the system state from an erroneously
executing condition and recover the system.
6.6.2
General Purpose Timer
There is another application of the WDT, which is used as a simple, long period timer. When the
CONFIG bits WDTEN[3:0] (CONFIG4[7:4]) is FH, the WDT is initialized as a general purpose timer. In
this mode, WDTR and WIDPD are fully accessed via software.
F
LIRC
IDL (PCON.0)
PD (PCON.1)
WIDPD
WDTR
WDCLR
WDPS[2:0]
WDT counter
(6-bit)
clear
overflow
10 kHz
Internal
Oscillator
WDTF
WDT Interrupt
Pre-scalar
(1/1~1/256)
Figure 6.6-2 Watchdog Timer Block Diagram
The WDT starts running by setting WDTR as 1 and halts by clearing WDTR as 0. The WDTF flag will
