MS51
Dec. 17, 2019
Page
225
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
CAPCON4
– Input Capture Control 4
Regiser
Address
Reset Value
CAPCON4
F2H, all pages
0000_0000b
7
6
5
4
3
2
1
0
-
-
-
-
CAP23
CAP22
CAP21
CAP20
-
-
-
-
R/W
R/W
R/W
R/W
Bit
Name
Description
[3:0]
CAP2[3:0]
Input capture channel 2 input pin select
0000 = P1.2/IC0
0001 = P1.1/IC1
0010 = P1.0/IC2
0011 = P0.0/IC3
0100 = P0.4/IC3
0101 = P0.1/IC4
0110 = P0.3/IC5
0111 = P0.5/IC6
1000 = P1.5/IC7
others = P1.2/IC0
6.5.3
Timer3
Timer 3 is implemented simply as a 16-bit auto-reload, up-counting timer. The user can select the pre-
scale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine
its overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over
FFFFH, TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and
RL3 registers to be reloaded into the internal 16-bit counter. If ET3 (EIE1.1) is set as 1, Timer 3
interrupt service routine will be served. TF3 is auto-cleared by hardware after entering its interrupt
service routine.
Timer 3 can also be the baud rate clock source of both UARTs. For details, please see Section
6.8.2
RL3
TR3
(T3CON.3)
F
SYS
Internal 16-bit Counter
0
7
RH3
0
7
Timer 3
Overflow
Pre-scalar
(1/1~1/128)
T3PS[2:0]
(T3CON[2:0])
TF3
(T3CON.4)
Timer 3 Interrupt
Figure 6.5-8 Timer 3 Block Diagram
