MS51
Nov. 28, 2019
Page
424
of 491
Rev 1.00
MS51
32K
SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
Bit
Name
Description
3
SI
I
2
C interrupt flag
SI flag is set by hardware when one of 26 possible I
2
C status (besides F8H status) is entered. After SI
is set, the software should read I2STAT register to determine which step has been passed and take
actions for next step.
SI is cleared by software. Before the SI is cleared, the low period of I2C0_SCL line is stretched. The
transaction is suspended. It is useful for the slave device to deal with previous data bytes until ready
for receiving the next byte.
The serial transaction is suspended until SI is cleared by software. After SI is cleared, I
2
C bus will
continue to generate START or repeated START condition, STOP condition, 8-bit data, or so on
depending on the software configuration of controlling byte or bits. Therefore, user should take care of
it by preparing suitable setting of registers before SI is software cleared.
2
AA
Acknowledge assert flag
If the AA flag is set, an ACK (low level on I2C0_SDA) will be returned during the acknowledge clock
pulse of the I2C0_SCL line while the I
2
C device is a receiver or an own-address-matching slave.
If the AA flag is cleared, a NACK (high level on I2C0_SDA) will be returned during the acknowledge
clock pulse of the I2C0_SCL line while the I
2
C device is a receiver or an own-address-matching slave.
A device with its own AA flag cleared will ignore its own salve address and the General Call.
Consequently, SI will note be asserted and no interrupt is requested.
Note that if an addressed slave does not return an ACK under slave receiver mode or not receive an
ACK under slave transmitter mode, the slave device will become a not addressed slave. It cannot
receive any data until its AA flag is set and a master addresses it again.
There is a special case of I2STAT value C8H occurs under slave transmitter mode. Before the slave
device transmit the last data byte to the master, AA flag can be cleared as 0. Then after the last data
byte transmitted, the slave device will actively switch to not addressed slave mode of disconnecting
with the master. The further reading by the master will be all FFH.
1
-
Reserved
0
I2CPX
I
2
C pins select
0 = Assign I2C0_SCL to P1.3 and I2C0_SDA to P1.4.
1 = Assign I2C0_SCL to P0.2 and I2C0_SDA to P1.6.
Note that I
2
C pins will exchange immediately once setting or clearing this bit.
SCL
SDA
Hold time extend
Figure 6.11-15 Hold Time extend enable
